coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

1 participants
6716 discussions

Change in coreboot[master]: cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION
by Angel Pons (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61479 ) Change subject: cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d Gerrit-Change-Number: 61479 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 00:00:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [Untested]cpu/x86/mp.h: Implement a pre-SSE2 mfence
by build bot (Jenkins) (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Keith Hui, Branden Waldner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59766 ) Change subject: [Untested]cpu/x86/mp.h: Implement a pre-SSE2 mfence ...................................................................... Patch Set 3: Verified+1 (3 comments) File src/include/cpu/x86/mp.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139505): https://review.coreboot.org/c/coreboot/+/59766/comment/973bb21d_b3bd7784 PS3, Line 18: __asm__ __volatile__("mfence\t\n": : :"memory"); spaces required around that ':' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139505): https://review.coreboot.org/c/coreboot/+/59766/comment/b97f5bd8_bcac8942 PS3, Line 18: __asm__ __volatile__("mfence\t\n": : :"memory"); spaces required around that ':' (ctx:WxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139505): https://review.coreboot.org/c/coreboot/+/59766/comment/a851aac8_37606206 PS3, Line 20: __asm__ __volatile__("lock; addl $0,0(%%esp)": : : "memory"); spaces required around that ':' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/59766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Gerrit-Change-Number: 59766 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 00:00:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
by build bot (Jenkins) (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58700 ) Change subject: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG ...................................................................... Patch Set 2: (3 comments) File src/cpu/x86/smm/smm_module_handler.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139504): https://review.coreboot.org/c/coreboot/+/58700/comment/c4cee997_1ffc5452 PS2, Line 150: if (0) suspect code indent for conditional statements (8, 8) File src/cpu/x86/smm/smm_module_loader.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139504): https://review.coreboot.org/c/coreboot/+/58700/comment/39e45c73_b5b6aac0 PS2, Line 440: static int smm_load_module_aseg(const uintptr_t smram_base, const size_t smram_size, struct smm_loader_params *params); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139504): https://review.coreboot.org/c/coreboot/+/58700/comment/34d93ddb_9586b3b3 PS2, Line 620: static int smm_load_module_aseg(const uintptr_t smram_base, const size_t smram_size, struct smm_loader_params *params) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/58700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Gerrit-Change-Number: 58700 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jan 2022 23:59:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/i440bx: Use PARALLEL_MP
by Kyösti Mälkki (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Keith Hui, Branden Waldner, Angel Pons, Arthur Heymans, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59693 ) Change subject: nb/intel/i440bx: Use PARALLEL_MP ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59693/comment/84ff1c02_0214e0fd PS4, Line 13: increase > is increased Done File src/northbridge/intel/i440bx/northbridge.c: https://review.coreboot.org/c/coreboot/+/59693/comment/1300a51e_ead9b30e PS4, Line 6: #include <device/device.h> > I wouldn't remove this, `struct device` is used Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Gerrit-Change-Number: 59693 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 23:49:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/smm: Retype variables
by build bot (Jenkins) (Code Review) 31 Jan '22

31 Jan '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58697 ) Change subject: cpu/x86/smm: Retype variables ...................................................................... Patch Set 2: Verified+1 (3 comments) File src/cpu/x86/smm/smm_module_loader.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139501): https://review.coreboot.org/c/coreboot/+/58697/comment/6ac6d5bf_ba285457 PS2, Line 325: uintptr_t base; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139501): https://review.coreboot.org/c/coreboot/+/58697/comment/8a862d3c_ead9526b PS2, Line 325: uintptr_t base; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139501): https://review.coreboot.org/c/coreboot/+/58697/comment/d80ecd74_0d1699d7 PS2, Line 491: int smm_load_module(const uintptr_t smram_base, const size_t smram_size, struct smm_loader_params *params) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/58697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Gerrit-Change-Number: 58697 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 23:39:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [NOTFORMERGE] cpu/x86/smm: Drop SMM_LEGACY_ASEG
by Kyösti Mälkki (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61495 ) Change subject: [NOTFORMERGE] cpu/x86/smm: Drop SMM_LEGACY_ASEG ...................................................................... [NOTFORMERGE] cpu/x86/smm: Drop SMM_LEGACY_ASEG Change-Id: I4fffffa8d58656bf9881dd97dec6d52789f1c0d2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family15tn/Makefile.inc D src/cpu/amd/smm/Makefile.inc D src/cpu/amd/smm/smm_init.c M src/cpu/qemu-x86/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/smm/Makefile.inc D src/cpu/x86/smm/smihandler.c D src/cpu/x86/smm/smm.ld D src/cpu/x86/smm/smmhandler.S D src/cpu/x86/smm/smmrelocate.S D src/include/cpu/x86/smi_deprecated.h M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c D src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/Makefile.inc M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c D src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82801ix/smihandler.c 21 files changed, 3 insertions(+), 1,319 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61495/1 diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index ca51196..7f60cd9 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -9,4 +9,3 @@ smm-y += udelay.c subdirs-y += ../../mtrr -subdirs-$(CONFIG_SMM_LEGACY_ASEG) += ../../smm diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc deleted file mode 100644 index 97a6694..0000000 --- a/src/cpu/amd/smm/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ - -ramstage-y += smm_init.c diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c deleted file mode 100644 index 71cca82..0000000 --- a/src/cpu/amd/smm/smm_init.c +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <cpu/x86/smi_deprecated.h> -#include <string.h> - -void smm_init(void) -{ - msr_t msr, syscfg_orig, mtrr_aseg_orig; - - /* Back up MSRs for later restore */ - syscfg_orig = rdmsr(SYSCFG_MSR); - mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000); - - /* MTRR changes don't like an enabled cache */ - disable_cache(); - - msr = syscfg_orig; - - /* Allow changes to MTRR extended attributes */ - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - /* turn the extended attributes off until we fix - * them so A0000 is routed to memory - */ - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - /* set DRAM access to 0xa0000 */ - msr.lo = 0x18181818; - msr.hi = 0x18181818; - wrmsr(MTRR_FIX_16K_A0000, msr); - - /* enable the extended features */ - msr = syscfg_orig; - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - enable_cache(); - /* copy the real SMM handler */ - memcpy((void *)SMM_BASE, _binary_smm_start, - _binary_smm_end - _binary_smm_start); - wbinvd(); - disable_cache(); - - /* Restore SYSCFG and MTRR */ - wrmsr(SYSCFG_MSR, syscfg_orig); - wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); - enable_cache(); - - /* CPU MSR are set in CPU init */ -} - -void smm_init_completion(void) -{ -} diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 868009c..78698fd 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -36,6 +36,7 @@ config CPU_QEMU_X86_ASEG_SMM bool "SMM in ASEG" select SMM_ASEG + depends on CPU_QEMU_X86_PARALLEL_MP config CPU_QEMU_X86_TSEG_SMM bool "SMM in TSEG" diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index d5c688d..9d1f01a 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -98,7 +98,7 @@ config HAVE_SMI_HANDLER bool default n - depends on (SMM_ASEG || SMM_TSEG) + depends on (SMM_ASEG || SMM_TSEG) && PARALLEL_MP config NO_SMM bool @@ -114,13 +114,7 @@ default y depends on !(NO_SMM || SMM_ASEG) -config SMM_LEGACY_ASEG - bool - default y if HAVE_SMI_HANDLER && SMM_ASEG && LEGACY_SMP_INIT - help - SMM support without PARALLEL_MP, to be deprecated. - -if HAVE_SMI_HANDLER && !SMM_LEGACY_ASEG +if HAVE_SMI_HANDLER config SMM_MODULE_HEAP_SIZE hex diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 7780be2..696950b 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -3,7 +3,6 @@ #include <cpu/x86/cr.h> #include <cpu/x86/gdt.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/smi_deprecated.h> #include <acpi/acpi.h> #include <delay.h> #include <lib.h> @@ -391,9 +390,6 @@ if (is_smp_boot()) copy_secondary_start_to_lowest_1M(); - if (CONFIG(SMM_LEGACY_ASEG)) - smm_init(); - /* Initialize the bootstrap processor */ cpu_initialize(0); @@ -404,9 +400,6 @@ if (is_smp_boot()) wait_other_cpus_stop(cpu_bus); - if (CONFIG(SMM_LEGACY_ASEG)) - smm_init_completion(); - if (is_smp_boot()) recover_lowest_1M(); } diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index ea4639d..f5ea17d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -78,17 +78,3 @@ $(OBJCOPY_smm) -O binary $< $@ endif - -ifeq ($(CONFIG_SMM_LEGACY_ASEG),y) - -smm-y += smm.ld - -$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o - $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map - $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ - -smm-y += smmhandler.S -smm-y += smihandler.c - -endif # CONFIG_SMM_LEGACY_ASEG diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c deleted file mode 100644 index 0b262af..0000000 --- a/src/cpu/x86/smm/smihandler.c +++ /dev/null @@ -1,211 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <console/console.h> -#include <commonlib/region.h> -#include <cpu/x86/smm.h> -#include <cpu/x86/smi_deprecated.h> -#include <cpu/amd/amd64_save_state.h> -#include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/x86/legacy_save_state.h> - -#if CONFIG(SPI_FLASH_SMM) -#include <spi-generic.h> -#endif - -static int do_driver_init = 1; - -typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; - -/* SMI multiprocessing semaphore */ -static __attribute__((aligned(4))) volatile smi_semaphore smi_handler_status - = SMI_UNLOCKED; - -static int smi_obtain_lock(void) -{ - u8 ret = SMI_LOCKED; - - asm volatile ( - "movb %2, %%al\n" - "xchgb %%al, %1\n" - "movb %%al, %0\n" - : "=g" (ret), "=m" (smi_handler_status) - : "g" (SMI_LOCKED) - : "eax" - ); - - return (ret == SMI_UNLOCKED); -} - -static void smi_release_lock(void) -{ - asm volatile ( - "movb %1, %%al\n" - "xchgb %%al, %0\n" - : "=m" (smi_handler_status) - : "g" (SMI_UNLOCKED) - : "eax" - ); -} - -#define LAPIC_ID 0xfee00020 -static __always_inline unsigned long nodeid(void) -{ - return (*((volatile unsigned long *)(LAPIC_ID)) >> 24); -} - -void io_trap_handler(int smif) -{ - /* If a handler function handled a given IO trap, it - * shall return a non-zero value - */ - printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif); - - if (southbridge_io_trap_handler(smif)) - return; - - if (mainboard_io_trap_handler(smif)) - return; - - printk(BIOS_DEBUG, "Unknown function\n"); -} - -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - southbridge_smi_set_eos(); -} - -static u32 pci_orig; - -/** - * @brief Backup PCI address to make sure we do not mess up the OS - */ -static void smi_backup_pci_address(void) -{ - pci_orig = inl(0xcf8); -} - -/** - * @brief Restore PCI address previously backed up - */ -static void smi_restore_pci_address(void) -{ - outl(pci_orig, 0xcf8); -} - -static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) -{ - base += SMM_SAVE_STATE_BEGIN(arch_offset) - (node * 0x400); - return (void *)base; -} - -/* This returns the SMM revision from the savestate of CPU0, - which is assumed to be the same for all CPU's. See the memory - map in smmhandler.S */ -uint32_t smm_revision(void) -{ - return *(uint32_t *)(SMM_BASE + SMM_ENTRY_OFFSET * 2 - SMM_REVISION_OFFSET_FROM_TOP); -} - -void *smm_get_save_state(int cpu) -{ - switch (smm_revision()) { - case 0x00030002: - case 0x00030007: - return smm_save_state(SMM_BASE, SMM_LEGACY_ARCH_OFFSET, cpu); - case 0x00030100: - return smm_save_state(SMM_BASE, SMM_EM64T100_ARCH_OFFSET, cpu); - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - return smm_save_state(SMM_BASE, SMM_EM64T101_ARCH_OFFSET, cpu); - case 0x00020064: - case 0x00030064: - return smm_save_state(SMM_BASE, SMM_AMD64_ARCH_OFFSET, cpu); - } - - return NULL; -} - -bool smm_region_overlaps_handler(const struct region *r) -{ - const struct region r_smm = {SMM_BASE, SMM_DEFAULT_SIZE}; - - return region_overlap(&r_smm, r); -} - -/** - * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map - */ - -void smi_handler(void) -{ - unsigned int node; - - /* Are we ok to execute the handler? */ - if (!smi_obtain_lock()) { - /* For security reasons we don't release the other CPUs - * until the CPU with the lock is actually done - */ - while (smi_handler_status == SMI_LOCKED) { - asm volatile ( - ".byte 0xf3, 0x90\n" /* hint a CPU we are in - * spinlock (PAUSE - * instruction, REP NOP) - */ - ); - } - return; - } - - smi_backup_pci_address(); - - node = nodeid(); - - console_init(); - - printk(BIOS_SPEW, "\nSMI# #%d\n", node); - - /* Use smm_get_save_state() to see if the smm revision is supported */ - if (smm_get_save_state(node) == NULL) { - printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision()); - printk(BIOS_WARNING, "SMI# not supported on your CPU\n"); - /* Don't release lock, so no further SMI will happen, - * if we don't handle it anyways. - */ - return; - } - - /* Allow drivers to initialize variables in SMM context. */ - if (do_driver_init) { -#if CONFIG(SPI_FLASH_SMM) - spi_init(); -#endif - do_driver_init = 0; - } - - /* Call chipset specific SMI handlers. */ - southbridge_smi_handler(); - - smi_restore_pci_address(); - - smi_release_lock(); - - /* De-assert SMI# signal to allow another SMI */ - smi_set_eos(); -} - -/* Provide a default implementation for all weak handlers so that relocation - * entries in the modules make sense. Without default implementations the - * weak relocations w/o a symbol have a 0 address which is where the modules - * are linked at. */ -int __weak mainboard_io_trap_handler(int smif) { return 0; } -void __weak southbridge_smi_handler(void) {} -void __weak mainboard_smi_gpi(u32 gpi_sts) {} -int __weak mainboard_smi_apmc(u8 data) { return 0; } -void __weak mainboard_smi_sleep(u8 slp_typ) {} -void __weak mainboard_smi_finalize(void) {} diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld deleted file mode 100644 index e232028..0000000 --- a/src/cpu/x86/smm/smm.ld +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Maximum number of CPUs/cores */ -CPUS = 4; - -_ = ASSERT(CPUS >= CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS"); - -ENTRY(smm_handler_start); - -SECTIONS -{ - /* This is the actual SMM handler. - * - * We just put code, rodata, data and bss all in a row. - */ - . = 0xa0000; - .handler (.): { - _program = .; - /* Assembler stub */ - *(.handler) - - /* C code of the SMM handler */ - *(.text); - *(.text.*); - - /* C read-only data of the SMM handler */ - . = ALIGN(16); - *(.rodata) - *(.rodata.*) - - /* C read-write data of the SMM handler */ - . = ALIGN(4); - *(.data) - *(.data.*) - - /* C uninitialized data of the SMM handler */ - . = ALIGN(4); - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - - /* What is this? (Something we don't need with -fno-common.) */ - *(COMMON) - . = ALIGN(4); - _eprogram = .; - } - - /* We are using the ASEG interleaved to stuff the SMM handlers - * for all CPU cores in there. The jump table redirects the execution - * to the actual SMM handler - */ - . = 0xa8000 - (( CPUS - 1) * 0x400); - .jumptable : { - KEEP(*(.jumptable)); - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - *(.eh_frame) - *(.debug_*) - } -} diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S deleted file mode 100644 index 19793a0..0000000 --- a/src/cpu/x86/smm/smmhandler.S +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* NOTE: This handler assumes the SMM window goes from 0xa0000 - * to 0xaffff. In fact, at least on Intel Core CPUs (i945 chipset) - * the SMM window is 128K big, covering 0xa0000 to 0xbffff. - * So there is a lot of potential for growth in here. Let's stick - * to 64k if we can though. - */ - -#include <cpu/x86/lapic_def.h> -#include <cpu/x86/msr.h> - -/* - * +--------------------------------+ 0xaffff - * | Save State Map Node 0 | - * | Save State Map Node 1 | - * | Save State Map Node 2 | - * | Save State Map Node 3 | - * | ... | - * +--------------------------------+ 0xaf000 - * | | - * | | - * | | - * +--------------------------------+ 0xa8400 - * | SMM Entry Node 0 (+ stack) | - * +--------------------------------+ 0xa8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | - * | ... | - * +--------------------------------+ 0xa7400 - * | | - * | SMM Handler | - * | | - * +--------------------------------+ 0xa0000 - * - */ - -/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG - * at which smm_handler_start lives. At the moment the handler - * lives right at 0xa0000, so the offset is 0. - */ - -#define SMM_HANDLER_OFFSET 0x0000 - -#if ENV_X86_64 -.bss -ia32efer_backup_eax: -.long 0 -ia32efer_backup_edx: -.long 0 -#endif - -/* initially SMM is some sort of real mode. Let gcc know - * how to treat the SMM handler stub - */ - -.section ".handler", "a", @progbits - -.code16 - -/** - * SMM code to enable protected mode and jump to the - * C-written function void smi_handler(u32 smm_revision) - * - * All the bad magic is not all that bad after all. - */ -#define SMM_START 0xa0000 -#define SMM_END 0xb0000 -#if SMM_END <= SMM_START -#error invalid SMM configuration -#endif -.global smm_handler_start -smm_handler_start: -#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) - /* Check if the LAPIC register block overlaps with SMM. - * This block needs to work without data accesses because they - * may be routed into the LAPIC register block. - * Code accesses, on the other hand, are never routed to LAPIC, - * which is what makes this work in the first place. - */ - mov $LAPIC_BASE_MSR, %ecx - rdmsr - and $(~0xfff), %eax - sub $(SMM_START), %eax - cmp $(SMM_END - SMM_START), %eax - ja untampered_lapic -1: - /* emit "Crash" on serial */ - mov $(CONFIG_TTYS0_BASE), %dx - mov $'C', %al - out %al, (%dx) - mov $'r', %al - out %al, (%dx) - mov $'a', %al - out %al, (%dx) - mov $'s', %al - out %al, (%dx) - mov $'h', %al - out %al, (%dx) - /* now crash for real */ - ud2 -untampered_lapic: -#endif - movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx - lgdtl %cs:(%bx) - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Enable protected mode */ - ljmpl $0x08, $1f - -.code32 -1: - /* flush the cache after disabling it */ - wbinvd - - /* Use flat data segment */ - movw $0x10, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - xor %ax, %ax /* zero out the gs and fs segment index */ - movw %ax, %fs - movw %ax, %gs /* Will be used for cpu_info */ - - /* FIXME: Incompatible with X2APIC_SUPPORT. */ - /* Get this CPU's LAPIC ID */ - movl $(LAPIC_DEFAULT_BASE | LAPIC_ID), %esi - movl (%esi), %ecx - shr $24, %ecx - - /* This is an ugly hack, and we should find a way to read the CPU index - * without relying on the LAPIC ID. - */ -#if CONFIG(CPU_AMD_AGESA_FAMILY15_TN) - /* LAPIC IDs start from 0x10; map that to the proper core index */ - subl $0x10, %ecx -#endif - - /* calculate stack offset by multiplying the APIC ID - * by 1024 (0x400), and save that offset in ebp. - */ - shl $10, %ecx - movl %ecx, %ebp - - /* We put the stack for each core right above - * its SMM entry point. Core 0 starts at 0xa8000, - * we spare 0x10 bytes for the jump to be sure. - */ - movl $0xa8010, %eax - subl %ecx, %eax /* subtract offset, see above */ - movl %eax, %ebx /* Save bottom of stack in ebx */ - -#define SMM_STACK_SIZE (0x400 - 0x10) - /* clear stack */ - cld - movl %eax, %edi - movl $(SMM_STACK_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* set new stack */ - addl $SMM_STACK_SIZE, %ebx - movl %ebx, %esp - -#if ENV_X86_64 - /* Backup IA32_EFER. Preserves ebx. */ - movl $(IA32_EFER), %ecx - rdmsr - movl %eax, ia32efer_backup_eax - movl %edx, ia32efer_backup_edx - - /* Enable long mode. Preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - -#endif - /* Call C handler */ - call smi_handler - -#if ENV_X86_64 - /* - * The only reason to go back to protected mode is that RSM doesn't restore - * MSR registers and MSR IA32_EFER was modified by entering long mode. - * Drop to protected mode to safely operate on the IA32_EFER MSR. - */ - - /* Disable long mode. */ - #include <cpu/x86/64bit/exit32.inc> - - /* Restore IA32_EFER as RSM doesn't restore MSRs. */ - movl $(IA32_EFER), %ecx - movl ia32efer_backup_eax, %eax - movl ia32efer_backup_edx, %edx - wrmsr -#endif - - /* To return, just do rsm. It will "clean up" protected mode */ - rsm - -.code16 - -.align 4, 0xff - -smm_gdtptr16: - .word smm_gdt_end - smm_gdt - 1 - .long smm_gdt - smm_handler_start + 0xa0000 + SMM_HANDLER_OFFSET - -.code32 - -smm_gdt: - /* The first GDT entry can not be used. Keep it zero */ - .long 0x00000000, 0x00000000 - - /* gdt selector 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ - - /* gdt selector 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - - /* gdt selector 0x18, flat code segment (64-bit) */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xaf, 0x00 -smm_gdt_end: - - -.section ".jumptable", "a", @progbits - -/* This is the SMM jump table. All cores use the same SMM handler - * for simplicity. But SMM Entry needs to be different due to the - * save state area. The jump table makes sure all CPUs jump into the - * real handler on SMM entry. - */ - -/* This code currently supports up to 4 CPU cores. If more than 4 CPU cores - * shall be used, below table has to be updated, as well as smm.ld - */ - -/* GNU AS/LD will always generate code that assumes CS is 0xa000. In reality - * CS will be set to SMM_BASE[19:4] though. Knowing that the smm handler is the - * first thing in the ASEG, we do a far jump here, to set CS to 0xa000. - */ - -.code16 -jumptable: - /* core 3 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET -.align 1024, 0x00 - /* core 2 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET -.align 1024, 0x00 - /* core 1 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET -.align 1024, 0x00 - /* core 0 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET -.align 1024, 0x00 diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S deleted file mode 100644 index f7dcc39..0000000 --- a/src/cpu/x86/smm/smmrelocate.S +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// FIXME: Is this piece of code southbridge specific, or -// can it be cleaned up so this include is not required? -// It's needed right now because we get our DEFAULT_PMBASE from -// here. -#if CONFIG(SOUTHBRIDGE_INTEL_I82801DX) -#include <southbridge/intel/i82801dx/i82801dx.h> -#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX) -#include <southbridge/intel/i82801ix/i82801ix.h> -#else -#error "Southbridge needs SMM handler support." -#endif - -// ADDR32() macro -#include <arch/registers.h> - -#if !CONFIG(SMM_ASEG) -#error "Only use this file with ASEG." -#endif /* CONFIG_SMM_ASEG */ - -#define LAPIC_ID 0xfee00020 - -.global smm_relocation_start -.global smm_relocation_end - -/* initially SMM is some sort of real mode. */ -.code16 - -/** - * When starting up, x86 CPUs have their SMBASE set to 0x30000. However, - * this is not a good place for the SMM handler to live, so it needs to - * be relocated. - * Traditionally SMM handlers used to live in the A segment (0xa0000). - * With growing SMM handlers, more CPU cores, etc. CPU vendors started - * allowing to relocate the handler to the end of physical memory, which - * they refer to as TSEG. - * This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 ) - * - * Why 0x400? It is a safe value to cover the save state area per CPU. On - * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel - * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes - * bigger, effectively sizing our data structures 0x300 bytes. - * - * Example (with SMM handler living at 0xa0000): - * - * LAPICID SMBASE SMM Entry SAVE STATE - * 0 0xa0000 0xa8000 0xafd00 - * 1 0x9fc00 0xa7c00 0xaf900 - * 2 0x9f800 0xa7800 0xaf500 - * 3 0x9f400 0xa7400 0xaf100 - * 4 0x9f000 0xa7000 0xaed00 - * 5 0x9ec00 0xa6c00 0xae900 - * 6 0x9e800 0xa6800 0xae500 - * 7 0x9e400 0xa6400 0xae100 - * 8 0x9e000 0xa6000 0xadd00 - * 9 0x9dc00 0xa5c00 0xad900 - * 10 0x9d800 0xa5800 0xad500 - * 11 0x9d400 0xa5400 0xad100 - * 12 0x9d000 0xa5000 0xacd00 - * 13 0x9cc00 0xa4c00 0xac900 - * 14 0x9c800 0xa4800 0xac500 - * 15 0x9c400 0xa4400 0xac100 - * . . . . - * . . . . - * . . . . - * 31 0x98400 0xa0400 0xa8100 - * - * With 32 cores, the SMM handler would need to fit between - * 0xa0000-0xa0400 and the stub plus stack would need to go - * at 0xa8000-0xa8100 (example for core 0). That is not enough. - * - * This means we're basically limited to 16 CPU cores before - * we need to move the SMM handler to TSEG. - * - * Note: Some versions of Pentium M need their SMBASE aligned to 32k. - * On those the above only works for up to 2 cores. But for now we only - * care fore Core (2) Duo/Solo - * - */ - -smm_relocation_start: - /* Check revision to see if AMD64 style SMM_BASE - * Intel Core Solo/Duo: 0x30007 - * Intel Core2 Solo/Duo: 0x30100 - * Intel SandyBridge: 0x30101 - * AMD64: 0x3XX64 - * This check does not make much sense, unless someone ports - * SMI handling to AMD64 CPUs. - */ - - mov $0x38000 + 0x7efc, %ebx - ADDR32(mov) (%ebx), %al - cmp $0x64, %al - je 1f - - mov $0x38000 + 0x7ef8, %ebx - jmp smm_relocate -1: - mov $0x38000 + 0x7f00, %ebx - -smm_relocate: - /* Get this CPU's LAPIC ID */ - movl $LAPIC_ID, %esi - ADDR32(movl) (%esi), %ecx - shr $24, %ecx - - /* calculate offset by multiplying the - * APIC ID by 1024 (0x400) - */ - movl %ecx, %edx - shl $10, %edx - - movl $0xa0000, %eax - subl %edx, %eax /* subtract offset, see above */ - - ADDR32(movl) %eax, (%ebx) - - /* The next section of code is potentially southbridge specific */ - - /* Clear SMI status */ - movw $(DEFAULT_PMBASE + 0x34), %dx - inw %dx, %ax - outw %ax, %dx - - /* Clear PM1 status */ - movw $(DEFAULT_PMBASE + 0x00), %dx - inw %dx, %ax - outw %ax, %dx - - /* Set EOS bit so other SMIs can occur */ - movw $(DEFAULT_PMBASE + 0x30), %dx - inl %dx, %eax - orl $(1 << 1), %eax - outl %eax, %dx - - /* End of southbridge specific section. */ - -#if CONFIG(DEBUG_SMM_RELOCATION) - /* print [SMM-x] so we can determine if CPUx went to SMM */ - movw $CONFIG_TTYS0_BASE, %dx - mov $'[', %al - outb %al, %dx - mov $'S', %al - outb %al, %dx - mov $'M', %al - outb %al, %dx - outb %al, %dx - movb $'-', %al - outb %al, %dx - /* calculate ascii of CPU number. More than 9 cores? -> FIXME */ - movb %cl, %al - addb $'0', %al - outb %al, %dx - mov $']', %al - outb %al, %dx - mov $'\r', %al - outb %al, %dx - mov $'\n', %al - outb %al, %dx -#endif - - /* That's it. return */ - rsm -smm_relocation_end: diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h deleted file mode 100644 index 262aa0b..0000000 --- a/src/include/cpu/x86/smi_deprecated.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __X86_SMI_DEPRECATED_H__ -#define __X86_SMI_DEPRECATED_H__ - -void smm_init(void); -void smm_init_completion(void); - -/* Entry from smmhandler.S. */ -void smi_handler(void); - -#endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index ff10091..7d00573 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -11,9 +11,6 @@ ramstage-y += usb.c ramstage-y += usb2.c -ramstage-$(CONFIG_SMM_LEGACY_ASEG) += smi.c -ramstage-$(CONFIG_SMM_LEGACY_ASEG) += ../../../cpu/x86/smm/smmrelocate.S - smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 9864720..60f8e55 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -19,7 +19,6 @@ void i82801dx_enable(struct device *dev); void i82801dx_early_init(void); -void aseg_smm_lock(void); #endif diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index e125656..80a7c93 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -272,12 +272,6 @@ /* Initialize the High Precision Event Timers */ enable_hpet(dev); - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - if (CONFIG(SMM_LEGACY_ASEG)) - aseg_smm_lock(); } static void i82801dx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c deleted file mode 100644 index dd993ce..0000000 --- a/src/southbridge/intel/i82801dx/smi.c +++ /dev/null @@ -1,323 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <acpi/acpi.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <cpu/x86/smi_deprecated.h> -#include <string.h> -#include "i82801dx.h" - -void northbridge_write_smram(u8 smram); - -/* For intel/e7505. */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = PMBASE_ADDR; - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_DEBUG, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i>= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear ALT_GP_SMI_STS - * @return ALT_GP_SMI_STS register - */ -static u16 reset_alt_gp_smi_status(void) -{ - u16 reg16; - - reg16 = inl(pmbase + ALT_GP_SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg16, pmbase + ALT_GP_SMI_STS); - - return reg16; -} - -static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) -{ - int i; - printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i=15; i>= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i); - } - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -extern uint8_t smm_relocation_start, smm_relocation_end; -static void *default_smm_area = NULL; - -static void aseg_smm_relocate(void) -{ - u32 smi_en; - u16 pm1_en; - - printk(BIOS_DEBUG, "Initializing SMM handler..."); - - pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffc; - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - default_smm_area = backup_default_smm_area(); - - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - wbinvd(); - - printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - - /* Enable SMI generation: - * - on TCO events - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - */ - - smi_en = 0; /* reset SMI enables */ - smi_en |= TCO_EN; - smi_en |= APMC_EN; - if (CONFIG(DEBUG_PERIODIC_SMI)) - smi_en |= PERIODIC_EN; - smi_en |= SLP_SMI_EN; - smi_en |= BIOS_EN; - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); - - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local APIC is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - apm_control(APM_CNT_NOOP_SMI); -} - -static void aseg_smm_install(void) -{ - /* copy the real SMM handler */ - memcpy((void *)0xa0000, _binary_smm_start, - _binary_smm_end - _binary_smm_start); - wbinvd(); -} - -void smm_init(void) -{ - /* Put SMM code to 0xa0000 */ - aseg_smm_install(); - - /* Put relocation code to 0x38000 and relocate SMBASE */ - aseg_smm_relocate(); - - /* We're done. Make sure SMIs can happen! */ - smi_set_eos(); -} - -void smm_init_completion(void) -{ - restore_default_smm_area(default_smm_area); -} - -void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index d376622..ecde2ed 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -28,9 +28,6 @@ ramstage-y += madt.c endif -ramstage-$(CONFIG_SMM_LEGACY_ASEG) += smi.c -ramstage-$(CONFIG_SMM_LEGACY_ASEG) += ../../../cpu/x86/smm/smmrelocate.S - CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include endif diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 56f14b0..2b1b26a 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -158,8 +158,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -void aseg_smm_lock(void); - void i82801ix_early_init(void); void i82801ix_lpc_setup(void); void i82801ix_dmi_setup(void); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 0132ac5..91077af 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -374,12 +374,6 @@ i8259_configure_irq_trigger(9, 1); i82801ix_set_acpi_mode(dev); - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - if (CONFIG(SMM_LEGACY_ASEG)) - aseg_smm_lock(); } static void i82801ix_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c deleted file mode 100644 index 1abd8c5..0000000 --- a/src/southbridge/intel/i82801ix/smi.c +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <acpi/acpi.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <cpu/x86/smi_deprecated.h> -#include <string.h> -#include <southbridge/intel/common/pmutil.h> -#include "i82801ix.h" - -/* I945/GM45 */ -#define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -extern uint8_t smm_relocation_start, smm_relocation_end; -static void *default_smm_area = NULL; - -static void aseg_smm_relocate(void) -{ - u32 smi_en; - u16 pm1_en; - - printk(BIOS_DEBUG, "Initializing SMM handler..."); - - pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), D31F0_PMBASE) & - 0xfffc; - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); - if (smi_en & GBL_SMI_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - default_smm_area = backup_default_smm_area(); - - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - wbinvd(); - - printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - - /* Enable SMI generation: - * - on TCO events - * - on APMC writes (io 0xb2) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - */ - - smi_en = 0; /* reset SMI enables */ - smi_en |= TCO_EN; - smi_en |= APMC_EN; - if (CONFIG(DEBUG_PERIODIC_SMI)) - smi_en |= PERIODIC_EN; - smi_en |= BIOS_EN; - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); - - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local APIC is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - apm_control(APM_CNT_NOOP_SMI); -} - -static int smm_handler_copied = 0; - -static void aseg_smm_install(void) -{ - /* The first CPU running this gets to copy the SMM handler. But not all - * of them. - */ - if (smm_handler_copied) - return; - smm_handler_copied = 1; - - /* if we're resuming from S3, the SMM code is already in place, - * so don't copy it again to keep the current SMM state */ - - if (!acpi_is_wakeup_s3()) { - /* enable the SMM memory window */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); - - /* copy the real SMM handler */ - memcpy((void *)0xa0000, _binary_smm_start, - _binary_smm_end - _binary_smm_start); - wbinvd(); - } - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - G_SMRAME | C_BASE_SEG); -} - -void smm_init(void) -{ - /* Put SMM code to 0xa0000 */ - aseg_smm_install(); - - /* Put relocation code to 0x38000 and relocate SMBASE */ - aseg_smm_relocate(); - - /* We're done. Make sure SMIs can happen! */ - smi_set_eos(); -} - -void smm_init_completion(void) -{ - restore_default_smm_area(default_smm_area); -} - -void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index e02b396..6da712c 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -9,11 +9,6 @@ #include <soc/nvs.h> -#if CONFIG(SMM_LEGACY_ASEG) -/* For qemu/x86-q35 to build properly. */ -struct global_nvs *gnvs; -#endif - int southbridge_io_trap_handler(int smif) { switch (smif) { -- To view, visit https://review.coreboot.org/c/coreboot/+/61495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fffffa8d58656bf9881dd97dec6d52789f1c0d2 Gerrit-Change-Number: 61495 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [WIP]mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
by Kyösti Mälkki (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/61494 to review the following change. Change subject: [WIP]mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG ...................................................................... [WIP]mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-q35/cpu.c 3 files changed, 34 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/61494/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 73aadfb..868009c 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -10,7 +10,6 @@ if CPU_QEMU_X86 -# coreboot i440fx does not support SMM choice prompt "AP init" default CPU_QEMU_X86_LAPIC_INIT @@ -24,6 +23,7 @@ endchoice +# coreboot i440fx does not support SMM choice prompt "SMM support" default CPU_QEMU_X86_ASEG_SMM @@ -35,7 +35,6 @@ config CPU_QEMU_X86_ASEG_SMM bool "SMM in ASEG" - depends on CPU_QEMU_X86_LAPIC_INIT select SMM_ASEG config CPU_QEMU_X86_TSEG_SMM diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 06aa83a..b55ace0 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -247,7 +247,7 @@ void mp_init_cpus(struct bus *cpu_bus) { - const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm; + const struct mp_ops *ops = CONFIG(NO_SMM) ? &mp_ops_no_smm : &mp_ops_with_smm; /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, ops); diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index fb31fc5..1504f2d 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <console/console.h> #include <cpu/x86/mp.h> #include <stdint.h> @@ -7,12 +9,41 @@ #include <cpu/amd/amd64_save_state.h> #include <mainboard/emulation/qemu-i440fx/fw_cfg.h> +#include <device/pci_ops.h> + +#include <mainboard/emulation/qemu-i440fx/memory.h> +#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/x86/smm.h> + +#include "q35.h" + +/* QEMU-specific register */ +#define EXT_TSEG_MBYTES 0x50 +#define SMRAMC 0x9d +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define G_SMRAME (1 << 3) +#define D_LCK (1 << 4) +#define D_CLS (1 << 5) +#define D_OPEN (1 << 6) +#define ESMRAMC 0x9e +#define T_EN (1 << 0) +#define TSEG_SZ_MASK (3 << 1) +#define H_SMRAME (1 << 7) + static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + if (CONFIG(SMM_TSEG)) + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (CONFIG(SMM_ASEG)) { + pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, G_SMRAME | C_BASE_SEG | D_OPEN); + *perm_smbase = 0xa0000; + *perm_smsize = 0x10000; + } /* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */ *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -- To view, visit https://review.coreboot.org/c/coreboot/+/61494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Gerrit-Change-Number: 61494 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: nb/intel/i440bx: Use PARALLEL_MP
by Kyösti Mälkki (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Keith Hui, Branden Waldner, Angel Pons, Kyösti Mälkki, Patrick Rudolph. Kyösti Mälkki has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59693 ) Change subject: nb/intel/i440bx: Use PARALLEL_MP ...................................................................... nb/intel/i440bx: Use PARALLEL_MP Now that PARALLEL_MP can also deal with !SMP it can be used for this northbridge, which always features one CPU. The ramstage size is decreased by roughly 5K, but the compressed size increased by ~1K. Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i440bx/northbridge.c 2 files changed, 15 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59693/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Gerrit-Change-Number: 59693 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
by Kyösti Mälkki (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Kyösti Mälkki. Kyösti Mälkki has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58700 ) Change subject: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG ...................................................................... [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG This will allow to migrate all platform to the parallel_mp init code and drop the old lapic_init code. Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c 4 files changed, 118 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/58700/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Gerrit-Change-Number: 58700 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/smm: Add SMM_LEGACY_ASEG
by Kyösti Mälkki (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61480 to look at the new patch set (#2). Change subject: cpu/x86/smm: Add SMM_LEGACY_ASEG ...................................................................... cpu/x86/smm: Add SMM_LEGACY_ASEG Followup will allow use of PARALLEL_MP with SMM_ASEG so some guards needs to be adjusted. Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/smm/Makefile.inc M src/cpu/x86/Kconfig M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/smi_deprecated.h M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801ix/Makefile.inc M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c 10 files changed, 19 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61480/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Gerrit-Change-Number: 61480 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2022