coreboot-gerrit January 2022

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Subrata Banik (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Nico Huber, Sridhar Siricilla, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/1de304b4_0d717868 PS2, Line 666: is_cse_fw_update_enabled WDYT about this ? static bool is_cse_fw_update_enabled(void) { if (CONFIG(SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE) && CONFIG(SOC_INTEL_CSE_RW_UPDATE) ) return !is_debug_cse_fw_update_disable(); return false; } -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 20:12:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/02cc8073_33be81b8 PS1, Line 670: } > You can easily avoid the weak function by not calling it […] Ack. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 19:43:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61380 to look at the new patch set (#2). Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... soc/inte/common: Add support to control coreboot and Intel SoC features The patch adds a framework to control coreboot and Intel SoC features dynamically. BIOS reads control information from OEM Section in the Descriptor Region and control the developer selected features. With the feature, debug team can control the selected SoC and coreboot features without rebuilding the coreboot. In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has to be selcted from mainboard. The OEM section starts from offset:0xf00 till end of the Descriptor Region. This patch adds support to control CSE firmware update functionality. BUG=b:153410586 TEST=Verified CSE firmware update functionality on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 --- M src/soc/intel/common/block/cse/cse_lite.c A src/soc/intel/common/block/debug/Kconfig A src/soc/intel/common/block/debug/Makefile.inc A src/soc/intel/common/block/debug/debug_feature.c A src/soc/intel/common/block/include/intelblocks/debug_feature.h 5 files changed, 82 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61380/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Define enum cpu_type type for core types
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61459 ) Change subject: soc/intel/common: Define enum cpu_type type for core types ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/61459/comment/473d6690_9b355fd3 PS2, Line 14: /* core types */ > The comment seems superfluous as the enum name is the same. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e Gerrit-Change-Number: 61459 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 19:35:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Define enum cpu_type type for core types
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61459 ) Change subject: soc/intel/common: Define enum cpu_type type for core types ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/61459/comment/c4deaba2_03641ed4 PS2, Line 14: /* core types */ > The comment seems superfluous as the enum name is the same. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e Gerrit-Change-Number: 61459 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 18:30:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Define enum cpu_type type for core types
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Patrick Rudolph. Hello Maulik V Vaghela, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61459 to look at the new patch set (#3). Change subject: soc/intel/common: Define enum cpu_type type for core types ...................................................................... soc/intel/common: Define enum cpu_type type for core types The patch defines enum values for small and big cores and uses them to indicate the big or small core. TEST=Verify the build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61459/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e Gerrit-Change-Number: 61459 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google, soc/intel: TEST Disable unused ports and TME
by Ravindra (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Sridhar Siricilla. Ravindra has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/61492 ) Change subject: mb/google, soc/intel: TEST Disable unused ports and TME ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/61492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f254df53c9fec117ee39d0c54e02116c4d7c103 Gerrit-Change-Number: 61492 Gerrit-PatchSet: 1 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google, soc/intel: TEST Disable unused ports and TME
by Ravindra (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla. Ravindra has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/61492 ) Change subject: mb/google, soc/intel: TEST Disable unused ports and TME ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/61492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f254df53c9fec117ee39d0c54e02116c4d7c103 Gerrit-Change-Number: 61492 Gerrit-PatchSet: 1 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google, soc/intel: TEST Disable unused ports and TME
by ravindr1 (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Sridhar Siricilla. Hello Sridhar Siricilla, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/61492 to review the following change. Change subject: mb/google, soc/intel: TEST Disable unused ports and TME ...................................................................... mb/google, soc/intel: TEST Disable unused ports and TME Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I1f254df53c9fec117ee39d0c54e02116c4d7c103 --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/61492/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index ee0fbce..585f418 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -22,6 +22,9 @@ # Enable CNVi BT register "CnviBtCore" = "true" + #Enable Total Memory Encryption + register "enable_tme" = "true" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 23071fe..ccf41e5 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -38,6 +38,9 @@ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "enable_tme" = "0 + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -69,6 +72,10 @@ }, }" device domain 0 on + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref dtt on chip drivers/intel/dptf ## sensor information @@ -121,6 +128,7 @@ device generic 0 on end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a5543d6..24b3306 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -559,6 +559,11 @@ * Default 0. Setting this to 1 enable CNVi DDR RFIM. */ bool CnviDdrRfim; + + /* Total Memory Encryption + * Defaults to 0. Setting this to 1 to enable TME. + */ + bool enable_tme; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 790aa99..f030108 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -165,7 +165,7 @@ { /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - m_cfg->TmeEnable = CONFIG(INTEL_TME); + m_cfg->TmeEnable = config->enable_tme; } static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/61492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f254df53c9fec117ee39d0c54e02116c4d7c103 Gerrit-Change-Number: 61492 Gerrit-PatchSet: 1 Gerrit-Owner: ravindr1 <ravindra(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/d0eeaaeb_41fb6442 PS15, Line 246: send_end_of_post_to_cse > > As per ME BWG, BIOS should avoid sending EOP command during S3 resume. […] Got it 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 15 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 30 Jan 2022 13:44:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2022