coreboot-gerrit January 2022

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Change in coreboot[master]: soc/intel/elkhartlake: Drop stale eNEM TODO comment
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Werner Zeh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61454 ) Change subject: soc/intel/elkhartlake: Drop stale eNEM TODO comment ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Gerrit-Change-Number: 61454 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 07:17:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Use pcr write to disable HECI1
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61433 ) Change subject: soc/intel/skylake: Use pcr write to disable HECI1 ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61433/comment/0f9fdbfb_2e956d31 PS6, Line 7: pcr nit: PCR? https://review.coreboot.org/c/coreboot/+/61433/comment/c2561006_aed8a644 PS6, Line 10: pcr nit: PCR? -- To view, visit https://review.coreboot.org/c/coreboot/+/61433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Gerrit-Change-Number: 61433 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 30 Jan 2022 07:17:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD
by Sridhar Siricilla (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61455 ) Change subject: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/61455/comment/52c2584f_7aa53ebd PS3, Line 589: Heci1 nit: HECI1. HECI is an abbreviation of "Host Embedded Controller Interface". -- To view, visit https://review.coreboot.org/c/coreboot/+/61455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Gerrit-Change-Number: 61455 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 30 Jan 2022 07:15:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Add SMM_LEGACY_ASEG
by Kyösti Mälkki (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61480 ) Change subject: cpu/x86/smm: Add SMM_LEGACY_ASEG ...................................................................... cpu/x86/smm: Add SMM_LEGACY_ASEG Followup will allow use of PARALLEL_MP with SMM_ASEG so some guards needs to be adjusted. Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/smm/Makefile.inc M src/cpu/x86/Kconfig M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/smi_deprecated.h M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801ix/Makefile.inc M src/southbridge/intel/i82801ix/lpc.c 9 files changed, 18 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61480/1 diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index a591447..ca51196 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -9,4 +9,4 @@ smm-y += udelay.c subdirs-y += ../../mtrr -subdirs-y += ../../smm +subdirs-$(CONFIG_SMM_LEGACY_ASEG) += ../../smm diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc index a645122..97a6694 100644 --- a/src/cpu/amd/smm/Makefile.inc +++ b/src/cpu/amd/smm/Makefile.inc @@ -1,2 +1,2 @@ -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_init.c +ramstage-y += smm_init.c diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index d021564..86f31e0 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -114,6 +114,12 @@ default y depends on !(NO_SMM || SMM_ASEG) +config SMM_LEGACY_ASEG + bool + default y if HAVE_SMI_HANDLER && SMM_ASEG && LEGACY_SMP_INIT + help + SMM support without PARALLEL_MP, to be deprecated. + if SMM_TSEG config SMM_MODULE_HEAP_SIZE diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 5f2b27b..7780be2 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -391,7 +391,8 @@ if (is_smp_boot()) copy_secondary_start_to_lowest_1M(); - smm_init(); + if (CONFIG(SMM_LEGACY_ASEG)) + smm_init(); /* Initialize the bootstrap processor */ cpu_initialize(0); @@ -403,7 +404,8 @@ if (is_smp_boot()) wait_other_cpus_stop(cpu_bus); - smm_init_completion(); + if (CONFIG(SMM_LEGACY_ASEG)) + smm_init_completion(); if (is_smp_boot()) recover_lowest_1M(); diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h index 6213915..262aa0b 100644 --- a/src/include/cpu/x86/smi_deprecated.h +++ b/src/include/cpu/x86/smi_deprecated.h @@ -3,16 +3,8 @@ #ifndef __X86_SMI_DEPRECATED_H__ #define __X86_SMI_DEPRECATED_H__ -#include <stdint.h> - -#if CONFIG(PARALLEL_MP) || !CONFIG(HAVE_SMI_HANDLER) -/* Empty stubs for platforms without SMI handlers. */ -static inline void smm_init(void) { } -static inline void smm_init_completion(void) { } -#else void smm_init(void); void smm_init_completion(void); -#endif /* Entry from smmhandler.S. */ void smi_handler(void); diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 030f7b4..ff10091 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -11,10 +11,8 @@ ramstage-y += usb.c ramstage-y += usb2.c -ifeq ($(CONFIG_SMM_ASEG),y) -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S -endif +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += smi.c +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += ../../../cpu/x86/smm/smmrelocate.S smm-y += smihandler.c diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 34d93c4..e125656 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -276,7 +276,7 @@ /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP)) + if (CONFIG(SMM_LEGACY_ASEG)) aseg_smm_lock(); } diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index dada885..d376622 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -28,10 +28,8 @@ ramstage-y += madt.c endif -ifeq ($(CONFIG_SMM_ASEG),y) -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S -endif +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += smi.c +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += ../../../cpu/x86/smm/smmrelocate.S CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 21f1faa..0132ac5 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -378,7 +378,7 @@ /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP)) + if (CONFIG(SMM_LEGACY_ASEG)) aseg_smm_lock(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Gerrit-Change-Number: 61480 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION
by Kyösti Mälkki (Code Review) 30 Jan '22

30 Jan '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61479 ) Change subject: cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION ...................................................................... cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION It was only evaluated on LEGACY_SMP_INIT path while model_106cx has used PARALLEL_MP for a long time. Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_106cx/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/lapic_cpu_init.c 3 files changed, 1 insertion(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/61479/1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 76e0423..85f6288 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -8,6 +8,5 @@ select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS - select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 13ff65d..d021564 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -147,17 +147,6 @@ default y if NORTHBRIDGE_INTEL_IRONLAKE default n -config SERIALIZED_SMM_INITIALIZATION - bool - default n - help - On some CPUs, there is a race condition in SMM. - This can occur when both hyperthreads change SMM state - variables in parallel without coordination. - Setting this option serializes the SMM initialization - to avoid an ugly hang in the boot process at the cost - of a slightly longer boot time. - config X86_AMD_FIXED_MTRRS bool default n diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index c35888a..5f2b27b 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -332,37 +332,6 @@ } -static void smm_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) -{ - struct device *cpu; - int pre_count = atomic_read(&active_cpus); - - /* Loop through the cpus once to let them run through SMM relocator */ - - for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { - if (cpu->path.type != DEVICE_PATH_APIC) - continue; - - printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n", - cpu->path.apic.apic_id); - - if (cpu == bsp_cpu) - continue; - - if (!cpu->enabled) - continue; - - if (!start_cpu(cpu)) - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU 0x%02x would not start!\n", - cpu->path.apic.apic_id); - - /* FIXME: endless loop */ - while (atomic_read(&active_cpus) != pre_count) - ; - } -} - static void wait_other_cpus_stop(struct bus *cpu_bus) { struct device *cpu; @@ -422,8 +391,7 @@ if (is_smp_boot()) copy_secondary_start_to_lowest_1M(); - if (!CONFIG(SERIALIZED_SMM_INITIALIZATION)) - smm_init(); + smm_init(); /* Initialize the bootstrap processor */ cpu_initialize(0); @@ -435,18 +403,6 @@ if (is_smp_boot()) wait_other_cpus_stop(cpu_bus); - if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) { - /* At this point, all APs are sleeping: - * smm_init() will queue a pending SMI on all cpus - * and smm_other_cpus() will start them one by one */ - smm_init(); - - if (is_smp_boot()) { - last_cpu_index = 0; - smm_other_cpus(cpu_bus, info->cpu); - } - } - smm_init_completion(); if (is_smp_boot()) -- To view, visit https://review.coreboot.org/c/coreboot/+/61479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d Gerrit-Change-Number: 61479 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/**/Kconfig: Properly override `DISABLE_HECI1_AT_PRE_BOOT`
by HAOUAS Elyes (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Felix Singer, Nico Huber, Tim Wawrzynczak, Angel Pons. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61478 ) Change subject: mb/**/Kconfig: Properly override `DISABLE_HECI1_AT_PRE_BOOT` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d447e73f672877c76eecea1eb8b8f41f89ce686 Gerrit-Change-Number: 61478 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jan 2022 06:34:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: isolate leaking config directive from src/mainboard/asus/h61-series/K...
by Idwer Vollering (Code Review) 30 Jan '22

30 Jan '22

Idwer Vollering has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61476 ) Change subject: isolate leaking config directive from src/mainboard/asus/h61-series/Kconfig ...................................................................... Abandoned 'superseded' in https://review.coreboot.org/c/coreboot/+/61477/ -- To view, visit https://review.coreboot.org/c/coreboot/+/61476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fd24923dd8d36adbe861515ce6c903697ef90d Gerrit-Change-Number: 61476 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/mediatek/mt8186: Support DRAM fast calibration using blob
by Paul Menzel (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61133 ) Change subject: soc/mediatek/mt8186: Support DRAM fast calibration using blob ...................................................................... Patch Set 25: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61133/comment/34a7a912_11cecc69 PS25, Line 15: Starting with MT8186 the implementation of fast calibration may need : to be changed, and a "DRAM blob" only path is introduced for devices : that has to do both full and fast calibration using the external blob. > Paul, does this sound good to you? Yes, thank you. Minor nit: … that have to do … -- To view, visit https://review.coreboot.org/c/coreboot/+/61133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc Gerrit-Change-Number: 61133 Gerrit-PatchSet: 25 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 29 Jan 2022 20:02:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/cs35l53: Add driver for generating device in SSDT
by Paul Menzel (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Patrick Georgi, Furquan Shaikh, Vitaly Rodionov, Tim Wawrzynczak, Marco Chen, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61448 ) Change subject: drivers/i2c/cs35l53: Add driver for generating device in SSDT ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61448/comment/eaa30917_26618d96 PS2, Line 8: Please start by describing the problem. Currently, the Linux driver does not work/shows an error? What is it? https://review.coreboot.org/c/coreboot/+/61448/comment/d8230f83_54068aa9 PS2, Line 11: the kernel. Is that documented in a datasheet? If so, please mention the name and revision. https://review.coreboot.org/c/coreboot/+/61448/comment/84626fb9_f2eb061b PS2, Line 12: Maybe paste the new log messages from coreboot, and mention on what device you tested this. -- To view, visit https://review.coreboot.org/c/coreboot/+/61448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606 Gerrit-Change-Number: 61448 Gerrit-PatchSet: 2 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 29 Jan 2022 19:59:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: IASL: Ignore IASL's "Missing dependency" warning
by HAOUAS Elyes (Code Review) 30 Jan '22

30 Jan '22

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59880 ) Change subject: IASL: Ignore IASL's "Missing dependency" warning ...................................................................... Patch Set 9: (2 comments) Patchset: PS9: > Ah, thanks. Would have sufficed to mention in the commit message that it's about […] we are using " $(IASL) $(IGNORED_IASL_WARNINGS) -we" meaning that IASL will report warnings as errors and will ignore "$(IGNORED_IASL_WARNINGS)" File src/mainboard/asus/h61-series/Kconfig: https://review.coreboot.org/c/coreboot/+/59880/comment/9a44e629_f375e870 PS9, Line 4: def_bool y > See CB:61477 indeed , thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/59880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28b437194f08232727623009372327fec15215dd Gerrit-Change-Number: 59880 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 29 Jan 2022 19:47:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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