coreboot-gerrit January 2022

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Change in coreboot[master]: soc/intel/cannonlake: Use SBI msg to disable HECI1
by Subrata Banik (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Wonkyu Kim, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Hello Wonkyu Kim, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61451 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Use SBI msg to disable HECI1 ...................................................................... soc/intel/cannonlake: Use SBI msg to disable HECI1 Select HECI_DISABLE_USING_SMM config for Cannon Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/smihandler.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/61451/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 Gerrit-Change-Number: 61451 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Choose SBI msg to disable HECI1
by Subrata Banik (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Wonkyu Kim, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61451 ) Change subject: soc/intel/cannonlake: Choose SBI msg to disable HECI1 ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61451/comment/c9d73eaa_3802d786 PS3, Line 7: Choose > nit:Use? Ack https://review.coreboot.org/c/coreboot/+/61451/comment/acb2d4d6_129de99d PS3, Line 9: on Cannonlake to perform heci1 : disabling using SBI msg inside SMM > my miss, I supposed to mention SMM 😊 . […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 Gerrit-Change-Number: 61451 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 29 Jan 2022 09:59:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Use pcr write to disable HECI1
by Subrata Banik (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Sridhar Siricilla, Werner Zeh, Andrey Petrov, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Werner Zeh, Andrey Petrov, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61444 to look at the new patch set (#5). Change subject: soc/intel/apollolake: Use pcr write to disable HECI1 ...................................................................... soc/intel/apollolake: Use pcr write to disable HECI1 Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Apollo Lake to disable HECI1 device using pcr writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/cse.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/61444/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e Gerrit-Change-Number: 61444 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Use pcr write to disable HECI1
by Subrata Banik (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Matt DeVillier, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61433 to look at the new patch set (#6). Change subject: soc/intel/skylake: Use pcr write to disable HECI1 ...................................................................... soc/intel/skylake: Use pcr write to disable HECI1 Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Skylake to disable HECI1 device using pcr writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61433/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Gerrit-Change-Number: 61433 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Rework heci_disable function
by Subrata Banik (Code Review) 29 Jan '22

29 Jan '22

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Change in coreboot[master]: soc/intel/common/cse: Rework heci_disable function
by Subrata Banik (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Maulik V Vaghela, Jonathan Zhang, Angel Pons, Sridhar Siricilla, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Nick Vaccaro, EricR Lai, Tim Chu. Hello build bot (Jenkins), Maulik V Vaghela, Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Nick Vaccaro, EricR Lai, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61431 to look at the new patch set (#7). Change subject: soc/intel/common/cse: Rework heci_disable function ...................................................................... soc/intel/common/cse: Rework heci_disable function This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 --- M src/soc/intel/alderlake/smihandler.c M src/soc/intel/apollolake/include/soc/pcr_ids.h M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/elkhartlake/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/tigerlake/smihandler.c M src/soc/intel/xeon_sp/include/soc/pcr_ids.h 13 files changed, 78 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Gerrit-Change-Number: 61431 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/lib/gcov-io.c: Fix indent for 'if' statement
by HAOUAS Elyes (Code Review) 29 Jan '22

29 Jan '22

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61475 ) Change subject: src/lib/gcov-io.c: Fix indent for 'if' statement ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/61475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f849f8cf52d2e92cad08f0c17b191c61261d145 Gerrit-Change-Number: 61475 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/lib/gcov-io.c: Fix indent for 'if' statement
by HAOUAS Elyes (Code Review) 29 Jan '22

29 Jan '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61475 ) Change subject: src/lib/gcov-io.c: Fix indent for 'if' statement ...................................................................... src/lib/gcov-io.c: Fix indent for 'if' statement Change-Id: I3f849f8cf52d2e92cad08f0c17b191c61261d145 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/gcov-io.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/61475/1 diff --git a/src/lib/gcov-io.c b/src/lib/gcov-io.c index e142524..0555707 100644 --- a/src/lib/gcov-io.c +++ b/src/lib/gcov-io.c @@ -149,8 +149,8 @@ { if (gcov_var.file) { #if !IN_GCOV - if (gcov_var.offset && gcov_var.mode < 0) - gcov_write_block(gcov_var.offset); + if (gcov_var.offset && gcov_var.mode < 0) + gcov_write_block(gcov_var.offset); #endif fclose(gcov_var.file); gcov_var.file = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/61475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f849f8cf52d2e92cad08f0c17b191c61261d145 Gerrit-Change-Number: 61475 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45/raminit.c: Fix indent for 'if' statement
by HAOUAS Elyes (Code Review) 29 Jan '22

29 Jan '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61474 ) Change subject: nb/intel/gm45/raminit.c: Fix indent for 'if' statement ...................................................................... nb/intel/gm45/raminit.c: Fix indent for 'if' statement Change-Id: I316ae56321da1183caefeac3163b8909d1a554b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/61474/1 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d990497..e7663b9 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -32,8 +32,8 @@ { sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); if ((sysinfo->stepping > STEPPING_B3) && - (sysinfo->stepping != STEPPING_CONVERSION_A1)) - die("Unknown stepping.\n"); + (sysinfo->stepping != STEPPING_CONVERSION_A1)) + die("Unknown stepping.\n"); if (sysinfo->stepping <= STEPPING_B3) printk(BIOS_DEBUG, "Stepping %c%d\n", 'A' + sysinfo->stepping / 4, sysinfo->stepping % 4); else -- To view, visit https://review.coreboot.org/c/coreboot/+/61474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I316ae56321da1183caefeac3163b8909d1a554b1 Gerrit-Change-Number: 61474 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/smsc/lpc47n207/early_serial.c: Fix indent for 'if' statement
by HAOUAS Elyes (Code Review) 29 Jan '22

29 Jan '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61473 ) Change subject: superio/smsc/lpc47n207/early_serial.c: Fix indent for 'if' statement ...................................................................... superio/smsc/lpc47n207/early_serial.c: Fix indent for 'if' statement Change-Id: I0342e25747458239c1ad8c0f70f91f700ae8325d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/smsc/lpc47n207/early_serial.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/61473/1 diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index 36f3b36..41d7860 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -57,7 +57,7 @@ outb(0x12, lpc_port); reg_value = inb(lpc_port + 1); if (reg_value != (lpc_port & 0xff)) - break; + break; outb(0x13, lpc_port); reg_value = inb(lpc_port + 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/61473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0342e25747458239c1ad8c0f70f91f700ae8325d Gerrit-Change-Number: 61473 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit January 2022