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Change subject: soc/mediatek/mt8186: Fix issue of clearing watchdog status
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61446/comment/ba322ed8_865d10c7
PS1, Line 9: .
is wrong in CB:58835.
https://review.coreboot.org/c/coreboot/+/61446/comment/75f5e63a_d9ef34d0
PS1, Line 9: Wrong implementation for
The implementation of
https://review.coreboot.org/c/coreboot/+/61446/comment/042e8e00_28d99a0a
PS1, Line 10: The setting value should be:
: value of wdt mode | 0x22000000.
The value written to the 'wdt_mode' register should be 'wdt_mode | 0x22000000' instead of 'wdt_status | 0x22000000'.
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Change subject: soc/mediatek/mt8186: Support DRAM fast calibration using blob
......................................................................
Patch Set 25: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61133/comment/7f8f1b0b_287db637
PS25, Line 15: Starting with MT8186 the implementation of fast calibration may need
: to be changed, and a "DRAM blob" only path is introduced for devices
: that has to do both full and fast calibration using the external blob.
Paul, does this sound good to you?
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 49: Verified+1
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139447):
https://review.coreboot.org/c/coreboot/+/57131/comment/27d880db_bd4efd67
PS49, Line 1895: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER);
line over 96 characters
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Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: util/lint/checkpatch.pl: Remove unneeded whitespaces and fix some typos
......................................................................
util/lint/checkpatch.pl: Remove unneeded whitespaces and fix some typos
This is to reduce difference with linux v5.16.
Change-Id: I4aa7abce83b41ccd5129717cd3bf85be19ec4807
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M util/lint/checkpatch.pl
1 file changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/61467/2
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Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
Patch Set 47:
(5 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/56773/comment/90741342_e3444983
PS46, Line 234: AMD_FW_PSP_TRUSTLETKEY
> not sure is this is needed in the PSP_LVL2_AB case; if so, please add. […]
AMD_FW_PSP_RECOVERY: not for A/B reocvery for sure.
AMD_FW_PSP_RTM_PUBKEY: not sure if A/B recovery need it.
https://review.coreboot.org/c/coreboot/+/56773/comment/fe78aff4_cb2f5d36
PS46, Line 236: AMD_FW_PSP_SMU_FIRMWARE
> all AMD_FW_PSP_SMU_FIRMWARE(2), AMD_SEC_GASKET and AMD_MP2_FW entries should likely be marked as PSP […]
Done
https://review.coreboot.org/c/coreboot/+/56773/comment/d149c5e6_bc35311d
PS46, Line 1755:
> when recovery_ab is set, i'd verify if multi_level is also set and possibly return an error with som […]
Done
if (cb_config.recovery_ab) {
cb_config.multi_level = true;
}
File util/amdfwtool/data_parse.c:
https://review.coreboot.org/c/coreboot/+/56773/comment/4fe06a38_79fc9fcd
PS46, Line 118: == 1
> since cb_config->recovery_ab is a boolean, the == 1 should probably be dropped here
Done
https://review.coreboot.org/c/coreboot/+/56773/comment/6a8476ac_57d92154
PS46, Line 125: cb_config->recovery_ab == 0
> !cb_config->recovery_ab
Done
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Change subject: amdfwtool: Add ISH header support for A/B recovery layout
......................................................................
Patch Set 40:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57747/comment/c4f817b1_849778b0
PS39, Line 9: ISH
> What is ISH?
Done
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I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Add ISH header support for A/B recovery layout
......................................................................
amdfwtool: Add ISH header support for A/B recovery layout
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
0x4A -> ISH B -> PSP L2 B -> BIOS L2 B
Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/Makefile
M util/amdfwtool/Makefile.inc
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
4 files changed, 63 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/57747/40
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I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
amdfwtool: Add support for AMD's BIOS A/B recovery feature
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
0x4A -> PSP L2 B -> BIOS L2 B
The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.
To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.
TEST=Majolica(Cezanne)
Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 216 insertions(+), 74 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56773/47
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