coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya: Add GPIO table for nissa
by Reka Norman (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Tim Wawrzynczak. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60995 ) Change subject: mb/google/brya: Add GPIO table for nissa ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Yeah, I think the only unresolved issues are checking the WWAN and SSD power sequencing requirements […] http://b/217092523, http://b/217092522 -- To view, visit https://review.coreboot.org/c/coreboot/+/60995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Gerrit-Change-Number: 60995 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 23:29:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
by Kangheui Won (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61126 ) Change subject: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Gerrit-Change-Number: 61126 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Jan 2022 22:57:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Kangheui Won (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Tim Wawrzynczak, Krishna P Bhat D. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 ) Change subject: mb/google/nissa: Add devicetree ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb: https://review.coreboot.org/c/coreboot/+/61141/comment/b44189a2_e03d76ed PS4, Line 112: device ref tcss_dma0 on end > Not applicable for ADL-N. Done https://review.coreboot.org/c/coreboot/+/61141/comment/4be84ab4_f094ee2b PS4, Line 113: device ref tcss_dma1 on end > Not applicable for ADL-N. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Sun, 30 Jan 2022 22:55:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Kangheui Won (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak. Hello build bot (Jenkins), Reka Norman, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61141 to look at the new patch set (#5). Change subject: mb/google/nissa: Add devicetree ...................................................................... mb/google/nissa: Add devicetree Fill in devicetree for nissa baseboard based on schematics. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb 1 file changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/61141/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: psp_verstage: report developer mode to PSP
by Kangheui Won (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61369 ) Change subject: psp_verstage: report developer mode to PSP ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/psp_verstage/chipset.c: https://review.coreboot.org/c/coreboot/+/61369/comment/a45a07ae_bc1e628d PS1, Line 39: svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); > When is CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE used? The enum includes all internal states in the PSP. PSP set it to UNSIGNED_VERSTAGE and ignore this svc if verstage is not signed. -- To view, visit https://review.coreboot.org/c/coreboot/+/61369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Gerrit-Change-Number: 61369 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 30 Jan 2022 22:47:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Kangheui Won (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... Patch Set 1: (2 comments) File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h: https://review.coreboot.org/c/coreboot/+/61368/comment/dea37eee_a745315d PS1, Line 53: #define SVC_SET_PLATFORM_BOOT_MODE 0x6C > nit: Why is 0x6B skipped? 0x6B was allocated for svc_set_fw_hash_table (CB:60289). It'll be dropped off cezanne but it'd be better to skip anyway. https://review.coreboot.org/c/coreboot/+/61368/comment/c9909725_2bb12129 PS1, Line 144: CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check > nit: I think CROS is more commonly used than CHROME_BOOK These types and enums come from header file in the PSP release. I think we should minimize difference to avoid confusion. -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 30 Jan 2022 22:44:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Drop stale eNEM TODO comment
by Subrata Banik (Code Review) 30 Jan '22

30 Jan '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61454 ) Change subject: soc/intel/elkhartlake: Drop stale eNEM TODO comment ...................................................................... soc/intel/elkhartlake: Drop stale eNEM TODO comment This patch drops stale TODO comment about enabling eNEM on EHL. eNEM is non-POR on the elkhartlake product. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61454 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved EricR Lai: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index b829602..7f8bca0 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -22,7 +22,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Gerrit-Change-Number: 61454 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Subrata Banik (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/e3ba7e3d_c059c545 PS15, Line 246: send_end_of_post_to_cse > Got it 👍 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 15 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 30 Jan 2022 21:22:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Upgrade CMake to 3.22.1 version
by Martin Roth - Personal (Code Review) 30 Jan '22

30 Jan '22

Attention is currently required from: Paul Menzel, HAOUAS Elyes. Martin Roth - Personal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59399 ) Change subject: crossgcc: Upgrade CMake to 3.22.1 version ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Removing `util/crossgcc/build-CMAKE` beforehand (left over from the failed LLVM 12. […] The problem is the normalize_dirs() function. Cmake doesn't need it, and it fails outside of the mechanism that marks the build as failed. I'll push a patch to fix that. -- To view, visit https://review.coreboot.org/c/coreboot/+/59399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4272f72dd6ed686dbad5615a0ab44c8c632b5930 Gerrit-Change-Number: 59399 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth - Personal <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 30 Jan 2022 20:54:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Allow limiting writes to SMM via CMOS
by Sean Rhodes (Code Review) 30 Jan '22

30 Jan '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61493 ) Change subject: soc/intel: Allow limiting writes to SMM via CMOS ...................................................................... soc/intel: Allow limiting writes to SMM via CMOS Allow using CMOS setting of "smm_bwp" to limit writes, in addition to the Kconfig option. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ibd1078a843258b737fe55a491e2b0b285fcabb03 --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/61493/1 diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 5ab0611..167dd02 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -66,7 +66,7 @@ fast_spi_set_bios_interface_lock_down(); /* Only allow writes in SMM */ - if (CONFIG(BOOTMEDIA_SMM_BWP)) { + if (CONFIG(BOOTMEDIA_SMM_BWP) || get_uint_option("smm_bwp", UINT_MAX)) { fast_spi_set_eiss(); fast_spi_enable_wp(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1078a843258b737fe55a491e2b0b285fcabb03 Gerrit-Change-Number: 61493 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit January 2022