coreboot-gerrit January 2022

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Change in coreboot[master]: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
by Reka Norman (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Reka Norman, Kangheui Won, Tim Wawrzynczak. Hello build bot (Jenkins), Reka Norman, Kangheui Won, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61496 to look at the new patch set (#3). Change subject: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 ...................................................................... mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 In the nivviks and nereid pre-proto builds, the memory straps used don't match those generated by spd_tools. Each pre-proto build only supports a single memory part, and each of these parts should have ID 0 (see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code the memory IDs to 0 instead of reading them from the memory strap pins. From P1 onwards, the memory straps will be assigned based on the IDs generated by spd_tools. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d --- M src/mainboard/google/brya/variants/nereid/Makefile.inc A src/mainboard/google/brya/variants/nereid/memory.c M src/mainboard/google/brya/variants/nivviks/Makefile.inc A src/mainboard/google/brya/variants/nivviks/memory.c 4 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/61496/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Gerrit-Change-Number: 61496 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
by Reka Norman (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Kangheui Won, Reka Norman, Tim Wawrzynczak. Hello build bot (Jenkins), Reka Norman, Kangheui Won, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61496 to look at the new patch set (#2). Change subject: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 ...................................................................... mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 In the nivviks and nereid pre-proto builds, the memory straps used don't match those generated by spd_tools. Each pre-proto build only supports a single memory part, and each of these parts should have ID 0 (see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code the memory IDs to 0 instead of reading them from the memory strap pins. From P1 onwards, the memory straps will be assigned based on the IDs generated by spd_tools. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d --- M src/mainboard/google/brya/variants/nereid/Makefile.inc A src/mainboard/google/brya/variants/nereid/memory.c M src/mainboard/google/brya/variants/nivviks/Makefile.inc A src/mainboard/google/brya/variants/nivviks/memory.c 4 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/61496/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Gerrit-Change-Number: 61496 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
by build bot (Jenkins) (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Reka Norman, Kangheui Won, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61496 ) Change subject: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/brya/variants/nereid/memory.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139517): https://review.coreboot.org/c/coreboot/+/61496/comment/01558f44_324c7ab3 PS1, Line 13: if (board_id() == 0) { braces {} are not necessary for single statement blocks File src/mainboard/google/brya/variants/nivviks/memory.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139517): https://review.coreboot.org/c/coreboot/+/61496/comment/80498a02_2dc865c0 PS1, Line 13: if (board_id() == 0) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/61496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Gerrit-Change-Number: 61496 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 02:44:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0
by Reka Norman (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Reka Norman. Hello Reka Norman, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/61496 to review the following change. Change subject: mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 ...................................................................... mb/google/brya: Override memory ID to 0 for nivviks and nereid P0 In the nivviks and nereid pre-proto builds, the memory straps used don't match those generated by spd_tools. Each pre-proto build only supports a single memory part, and each of these parts should have ID 0 (see CB:61443). Therefore, for nivviks and nereid board ID 0, hard code the memory IDs to 0 instead of reading them from the memory strap pins. From P1 onwards, the memory straps will be assigned based on the IDs generated by spd_tools. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d --- M src/mainboard/google/brya/variants/nereid/Makefile.inc A src/mainboard/google/brya/variants/nereid/memory.c M src/mainboard/google/brya/variants/nivviks/Makefile.inc A src/mainboard/google/brya/variants/nivviks/memory.c 4 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/61496/1 diff --git a/src/mainboard/google/brya/variants/nereid/Makefile.inc b/src/mainboard/google/brya/variants/nereid/Makefile.inc index 58c4d79..defb592 100644 --- a/src/mainboard/google/brya/variants/nereid/Makefile.inc +++ b/src/mainboard/google/brya/variants/nereid/Makefile.inc @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c + romstage-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nereid/memory.c b/src/mainboard/google/brya/variants/nereid/memory.c new file mode 100644 index 0000000..78b0a36 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> + +int variant_memory_sku(void) +{ + /* + * The memory straps in the P0 build don't match those generated by + * spd_tools, so override the memory ID to 0. + */ + if (board_id() == 0) { + return 0; + } + + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + diff --git a/src/mainboard/google/brya/variants/nivviks/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/Makefile.inc index 58c4d79..defb592 100644 --- a/src/mainboard/google/brya/variants/nivviks/Makefile.inc +++ b/src/mainboard/google/brya/variants/nivviks/Makefile.inc @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c + romstage-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nivviks/memory.c b/src/mainboard/google/brya/variants/nivviks/memory.c new file mode 100644 index 0000000..cd20f81 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> + +int variant_memory_sku(void) +{ + /* + * The memory straps in the P0 build don't match those generated by + * spd_tools, so override the memory ID to 0. + */ + if (board_id() == 0) { + return 0; + } + + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c6f3f22d7a94f9eed44e736308e5ac4157163d Gerrit-Change-Number: 61496 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add GPIO table for nissa
by Reka Norman (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60995 ) Change subject: mb/google/brya: Add GPIO table for nissa ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Added nivviks and nereid gpio.c to their Makefiles. -- To view, visit https://review.coreboot.org/c/coreboot/+/60995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Gerrit-Change-Number: 60995 Gerrit-PatchSet: 9 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 02:19:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add Alder Lake P IGD device IDs
by Casper Chang (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61441 ) Change subject: soc/intel/alderlake: Add Alder Lake P IGD device IDs ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Hi Tim, Would you please help to submit this change? -- To view, visit https://review.coreboot.org/c/coreboot/+/61441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Gerrit-Change-Number: 61441 Gerrit-PatchSet: 6 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 02:19:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add GPIO table for nissa
by Reka Norman (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak. Hello build bot (Jenkins), Reka Norman, Kangheui Won, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60995 to look at the new patch set (#9). Change subject: mb/google/brya: Add GPIO table for nissa ...................................................................... mb/google/brya: Add GPIO table for nissa Fill in the nissa baseboard GPIO table based on the nivviks P0 and nereid P0 schematics. Also, add an override GPIO table for each of nivviks and nereid. The differences between nivviks and nereid are: - WFC: nivviks has a MIPI WFC and nereid has a USB WFC, so the MIPI-related pins are overriden to NC on nereid. - The DMIC pins and speaker I2S pins were swapped after nivviks P0. The baseboard reflects the new configuration, which will be used in nivviks P1 onwards, nereid, and future variants. For now, nivviks overrides the pins to the old configuration. Once nivviks P1 is released, this will need to be updated to handle both. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c A src/mainboard/google/brya/variants/nereid/Makefile.inc A src/mainboard/google/brya/variants/nereid/gpio.c A src/mainboard/google/brya/variants/nivviks/Makefile.inc A src/mainboard/google/brya/variants/nivviks/gpio.c 5 files changed, 512 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60995/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/60995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Gerrit-Change-Number: 60995 Gerrit-PatchSet: 9 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add the Primary to Sideband bridge library
by John Zhao (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61283 ) Change subject: soc/intel/common: Add the Primary to Sideband bridge library ...................................................................... Patch Set 7: (1 comment) Patchset: PS5: > I'm good with this Can you please go ahead to approve this PR since no objection from others? We want to chain this PR as base and upstream other patches internally. -- To view, visit https://review.coreboot.org/c/coreboot/+/61283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Gerrit-Change-Number: 61283 Gerrit-PatchSet: 7 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 00:30:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Retype variables
by Angel Pons (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58697 ) Change subject: cpu/x86/smm: Retype variables ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/58697/comment/00e9ed59_bbec7766 PS2, Line 325: uintptr_t base; > code indent should use tabs where possible Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/58697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Gerrit-Change-Number: 58697 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 00:03:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Add SMM_LEGACY_ASEG
by Angel Pons (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61480 ) Change subject: cpu/x86/smm: Add SMM_LEGACY_ASEG ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61480/comment/83a0e68b_9a06a7ea PS2, Line 10: needs nit: need -- To view, visit https://review.coreboot.org/c/coreboot/+/61480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Gerrit-Change-Number: 61480 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 00:02:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2022