coreboot-gerrit January 2022

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Change in coreboot[master]: mb/google/brya/variant/agah: Update memory settings
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61313 ) Change subject: mb/google/brya/variant/agah: Update memory settings ...................................................................... mb/google/brya/variant/agah: Update memory settings Based on the agah schematic, add memory settings. BUG=b:215662929 TEST=none Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ib45241d708d025ca75ed06e2bcf3997558723a62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61313 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/agah/Makefile.inc A src/mainboard/google/brya/variants/agah/memory.c 2 files changed, 72 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/agah/Makefile.inc b/src/mainboard/google/brya/variants/agah/Makefile.inc index d38141c..139345f 100644 --- a/src/mainboard/google/brya/variants/agah/Makefile.inc +++ b/src/mainboard/google/brya/variants/agah/Makefile.inc @@ -3,4 +3,6 @@ romstage-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/agah/memory.c b/src/mainboard/google/brya/variants/agah/memory.c new file mode 100644 index 0000000..ef5e69a --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/memory.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 0, 1, 4, 7, 6, 5, }, /* DDR_A_DQ0 */ + .dq1 = { 12, 13, 14, 15, 9, 10, 8, 11, }, /* DDR_A_DQ1 */ + }, + .ddr1 = { + .dq0 = { 14, 8, 9, 15, 10, 12, 11, 13, }, /* DDR_A_DQ2 */ + .dq1 = { 1, 7, 6, 0, 5, 3, 4, 2, }, /* DDR_A_DQ3 */ + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 6, 5, 7, 4, }, /* DDR_A_DQ4 */ + .dq1 = { 12, 13, 14, 15, 10, 11, 9, 8, }, /* DDR_A_DQ5 */ + }, + .ddr3 = { + .dq0 = { 1, 2, 0, 3, 5, 6, 7, 4, }, /* DDR_A_DQ6 */ + .dq1 = { 15, 14, 13, 12, 10, 9, 8, 11, }, /* DDR_A_DQ7 */ + }, + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 7, 6, 5, 4, }, /* DDR_B_DQ0 */ + .dq1 = { 12, 15, 13, 14, 8, 9, 10, 11, }, /* DDR_B_DQ1 */ + }, + .ddr5 = { + .dq0 = { 14, 8, 9, 15, 12, 10, 11, 13, }, /* DDR_B_DQ2 */ + .dq1 = { 1, 7, 6, 0, 5, 2, 4, 3, }, /* DDR_B_DQ3 */ + }, + .ddr6 = { + .dq0 = { 13, 12, 15, 14, 8, 10, 9, 11, }, /* DDR_B_DQ4 */ + .dq1 = { 7, 4, 6, 5, 1, 0, 3, 2, }, /* DDR_B_DQ5 */ + }, + .ddr7 = { + .dq0 = { 6, 0, 7, 5, 3, 2, 1, 4, }, /* DDR_B_DQ6 */ + .dq1 = { 10, 8, 13, 12, 9, 14, 15, 11, }, /* DDR_B_DQ7 */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib45241d708d025ca75ed06e2bcf3997558723a62 Gerrit-Change-Number: 61313 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/adl: Update devicetree based on remapping for TBT PCIe
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61295 ) Change subject: soc/intel/adl: Update devicetree based on remapping for TBT PCIe ...................................................................... soc/intel/adl: Update devicetree based on remapping for TBT PCIe ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe coalescing logic where in case root port 0 is disabled, other enabled root port is remapped to port 0. coreboot handles this remapping scenarios for PCH and CPU PCIe root ports and not for TBT root ports. This patch uses the same function used for PCIe remapping to update devicetree based on coalescing and SoC needs to pass correct function number and number of slots. BUG=b:210933428 BRANCH=None TEST=Check if TBT remapping happens correctly and ACPI tables are generated correctly. Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pcie.h M src/soc/intel/alderlake/pcie_rp.c 4 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 89d0c93..dc7d32b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -207,6 +207,12 @@ default 0 if SOC_INTEL_ALDERLAKE_PCH_N default 3 if SOC_INTEL_ALDERLAKE_PCH_P +config MAX_TBT_ROOT_PORTS + int + default 0 if SOC_INTEL_ALDERLAKE_PCH_N + default 2 if SOC_INTEL_ALDERLAKE_PCH_M + default 4 if SOC_INTEL_ALDERLAKE_PCH_P + config MAX_ROOT_PORTS int default MAX_PCH_ROOT_PORTS diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 1fa78fb..9127c5e 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -142,6 +142,9 @@ /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pch_pcie_rp_table()); + + /* Swap enabled TBT root ports in device tree if needed. */ + pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); } static void cpu_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h index cd76d09..6b3ca54 100644 --- a/src/soc/intel/alderlake/include/soc/pcie.h +++ b/src/soc/intel/alderlake/include/soc/pcie.h @@ -7,5 +7,6 @@ const struct pcie_rp_group *get_pch_pcie_rp_table(void); const struct pcie_rp_group *get_cpu_pcie_rp_table(void); +const struct pcie_rp_group *get_tbt_pcie_rp_table(void); #endif /* __SOC_ALDERLAKE_PCIE_H__ */ diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index 26ce785..f38105a 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -61,6 +61,16 @@ return cpu_rp_groups; } +static const struct pcie_rp_group tbt_rp_groups[] = { + { .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS}, + { 0 } +}; + +const struct pcie_rp_group *get_tbt_pcie_rp_table(void) +{ + return tbt_rp_groups; +} + static bool is_part_of_group(const struct device *dev, const struct pcie_rp_group *groups) { 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Gerrit-Change-Number: 61295 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61331 ) Change subject: intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree ...................................................................... intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree pcie_rp_update_devicetree function takes pcie_rp_group strcuture as an argument and SoC code passes the parameter in this structure. This pointer can be NULL and common code may try to dereference this NULL pointer. Also, group might have no data and SoC may pass this by indicating group count as zero (For example, for CPU or TBT root ports). These checks will prevent function from executing redundant code and returning early from the call as it's not required. BUG=b:210933428 BRANCH=None TEST=check if function returns early for group count 0 and there is no issue while booting board in case group count = 0. Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61331 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/pcie/pcie_rp.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 1c69f2c..221ee03 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -130,6 +130,9 @@ int mapping[CONFIG_MAX_ROOT_PORTS]; unsigned int offset, i; + if (!groups || !groups->count) + return; + struct bus *const root = pci_root_bus(); if (!root) return; 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Gerrit-Change-Number: 61331 Gerrit-PatchSet: 8 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Create crota variant
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61416 ) Change subject: mb/google/brya: Create crota variant ...................................................................... mb/google/brya: Create crota variant Create the crota variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:215443524 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CROTA Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ic8f1a0bde286d5d014dfdf87c2a417ca6ff8b3a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61416 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/crota/include/variant/ec.h A src/mainboard/google/brya/variants/crota/include/variant/gpio.h A src/mainboard/google/brya/variants/crota/memory/Makefile.inc A src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/crota/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index cc2a882..e585f9f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -154,6 +154,7 @@ default "Agah" if BOARD_GOOGLE_AGAH default "Volmar" if BOARD_GOOGLE_VOLMAR default "Banshee" if BOARD_GOOGLE_BANSHEE + default "Crota" if BOARD_GOOGLE_CROTA config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -178,6 +179,7 @@ default "agah" if BOARD_GOOGLE_AGAH default "volmar" if BOARD_GOOGLE_VOLMAR default "banshee" if BOARD_GOOGLE_BANSHEE + default "crota" if BOARD_GOOGLE_CROTA config VBOOT select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 8fbd622..0a3b1d9 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -158,3 +158,7 @@ bool "-> Banshee" select BOARD_GOOGLE_BASEBOARD_BRYA select MEMORY_SODIMM + +config BOARD_GOOGLE_CROTA + bool "-> Crota" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/crota/include/variant/ec.h b/src/mainboard/google/brya/variants/crota/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/crota/include/variant/gpio.h b/src/mainboard/google/brya/variants/crota/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/crota/memory/Makefile.inc b/src/mainboard/google/brya/variants/crota/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/61416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8f1a0bde286d5d014dfdf87c2a417ca6ff8b3a3 Gerrit-Change-Number: 61416 Gerrit-PatchSet: 2 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: temp
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Bao Zheng, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61450 ) Change subject: temp ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: CB:61460 has fixed the bug -- To view, visit https://review.coreboot.org/c/coreboot/+/61450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5dbd1ca061fcc20e45dbc8fb1211a5a8144bbc Gerrit-Change-Number: 61450 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Mon, 31 Jan 2022 10:32:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Add variant to disable HDMI
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61361 ) Change subject: mb/amd/majolica: Add variant to disable HDMI ...................................................................... mb/amd/majolica: Add variant to disable HDMI For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61361 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/majolica/port_descriptors.c 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/port_descriptors.c b/src/mainboard/amd/majolica/port_descriptors.c index 9c771f4..4cbccf6 100644 --- a/src/mainboard/amd/majolica/port_descriptors.c +++ b/src/mainboard/amd/majolica/port_descriptors.c @@ -3,6 +3,7 @@ #include <soc/gpio.h> #include <soc/platform_descriptors.h> #include <types.h> +#include <amdblocks/cpu.h> static const fsp_dxio_descriptor majolica_czn_dxio_descriptors[] = { { /* MXM */ @@ -92,7 +93,7 @@ } }; -static const fsp_ddi_descriptor majolica_czn_ddi_descriptors[] = { +static fsp_ddi_descriptor majolica_czn_ddi_descriptors[] = { { /* DDI0 - DP */ .connector_type = DDI_DP, .aux_index = DDI_AUX1, @@ -124,6 +125,9 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { + if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) + majolica_czn_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; + *dxio_descs = majolica_czn_dxio_descriptors; *dxio_num = ARRAY_SIZE(majolica_czn_dxio_descriptors); *ddi_descs = majolica_czn_ddi_descriptors; -- To view, visit https://review.coreboot.org/c/coreboot/+/61361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Gerrit-Change-Number: 61361 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/guybrush: Add variant to disable HDMI
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61314 ) Change subject: mb/google/guybrush/guybrush: Add variant to disable HDMI ...................................................................... mb/google/guybrush/guybrush: Add variant to disable HDMI For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c BUG=b:215432928 Change-Id: I93fca8cf9870533da1bcca5fa28ff22085e65beb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61314 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/guybrush/variants/guybrush/variant.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c index 54ca6a0..974e357 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/variant.c +++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c @@ -4,6 +4,7 @@ #include <boardid.h> #include <device/device.h> #include <soc/gpio.h> +#include <amdblocks/cpu.h> bool variant_has_pcie_wwan(void) { @@ -14,3 +15,9 @@ { return board_id() == 1 ? GPIO_70 : GPIO_69; } + +void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) +{ + if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) + ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93fca8cf9870533da1bcca5fa28ff22085e65beb Gerrit-Change-Number: 61314 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZE
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61358 ) Change subject: soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZE ...................................................................... soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZE Commit 86302a806c5cc9b575424305e761753710417692 (soc/amd/{common, cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE) added this Kconfig option before the initial commit that added soc/amd/sabrina as copy of soc/amd/cezanne landed in the tree, so port the change forward to Sabrina. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61358 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/sabrina/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 5e0c71f..ca7a83c 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -130,6 +130,12 @@ started. The workbuf's base depends on the address of the reset vector. +config PRE_X86_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Size of the CBMEM console used in PSP verstage. + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 -- To view, visit https://review.coreboot.org/c/coreboot/+/61358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e Gerrit-Change-Number: 61358 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse: Make cse_disable_mei_devices a public function
by Sridhar Siricilla (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61430 ) Change subject: soc/intel/common/cse: Make cse_disable_mei_devices a public function ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/61430/comment/c956b9d5_52c52b3b PS3, Line 489: Function to make cse disable > Sorry, I don't think there is anything grammatically wrong here. […] I'm not hard on my comment, but the most comments are imperative statements. -- To view, visit https://review.coreboot.org/c/coreboot/+/61430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Gerrit-Change-Number: 61430 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:57:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Rework heci_disable function
by EricR Lai (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Maulik V Vaghela, Jonathan Zhang, Angel Pons, Sridhar Siricilla, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Tim Wawrzynczak, Christian Walter, Nick Vaccaro, Tim Chu. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61431 ) Change subject: soc/intel/common/cse: Rework heci_disable function ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Gerrit-Change-Number: 61431 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:55:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2022