coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

1 participants
6716 discussions

Change in coreboot[master]: psp_verstage: report developer mode to PSP
by Raul Rangel (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Marshall Dawson, Kangheui Won, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61369 ) Change subject: psp_verstage: report developer mode to PSP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Gerrit-Change-Number: 61369 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 16:15:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Raul Rangel (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... Patch Set 1: (1 comment) File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h: https://review.coreboot.org/c/coreboot/+/61368/comment/6016ec3f_b27e98c1 PS1, Line 144: CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check > Ack Reading the comment on the other CL, should we remove the values we aren't going to support? i.e., `CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE`. -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 16:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Raul Rangel (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 16:12:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Remove `mb_gpio_lock_config()` override function
by EricR Lai (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61503 ) Change subject: mb/google/brya: Remove `mb_gpio_lock_config()` override function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Gerrit-Change-Number: 61503 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 16:09:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 9: (4 comments) File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/6f27a75f_073463bd PS9, Line 34: help > depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2? can you please elaborate on why you are suggesting this dependency? File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/51ba9452_56faf2c9 PS9, Line 96: #define FUSE_STATUS_NOT_ALLOWED 0x09 : #define FUSE_STATUS_FUSING_ERR 0x0a : #define FUSE_STATUS_BOOT_DONE 0x0b > can be moved up. these are used in fuse_status_to_string(). https://review.coreboot.org/c/coreboot/+/60968/comment/9ebb4739_aa8e11bf PS9, Line 187: > extra tab. extra space is added to split of printk line. https://review.coreboot.org/c/coreboot/+/60968/comment/8b171740_18afdd50 PS9, Line 210: > extra tab. extra space is added to split of printk line. -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 9 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 15:50:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/haswell: Report SMBIOS memory frequency in MT/s
by Angel Pons (Code Review) 31 Jan '22

31 Jan '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61504 ) Change subject: nb/intel/haswell: Report SMBIOS memory frequency in MT/s ...................................................................... nb/intel/haswell: Report SMBIOS memory frequency in MT/s The memory frequency values in SMBIOS tables are expressed in MT/s, not MHz. Adjust the reported frequency values accordingly. Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/haswell_mrc/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/61504/1 diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index e46eb57..fedb683 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -234,7 +234,7 @@ memset(mem_info, 0, sizeof(struct memory_info)); - const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; + const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; for (ch = 0; ch < NUM_CHANNELS; ch++) { const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); @@ -246,7 +246,7 @@ dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; dimm->ddr_type = MEMORY_TYPE_DDR3; - dimm->ddr_frequency = ddr_frequency; + dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */ dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); dimm->channel_num = ch; dimm->dimm_num = d_num; -- To view, visit https://review.coreboot.org/c/coreboot/+/61504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Gerrit-Change-Number: 61504 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Lean Sheng Tan (Code Review) 31 Jan '22

31 Jan '22

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... Patch Set 12: (2 comments) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54959/comment/0df152a3_8b2e04e6 PS12, Line 54: _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= : ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); : memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, : sizeof(config->SerialIoI2cMode)); : > why? just why? see diskussion here about making the devicetree a mess https://review.coreboot. […] Yes soc device tree is a better idea. what is your take here? https://review.coreboot.org/c/coreboot/+/54959/comment/bb32b710_74430b4d PS12, Line 65: params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09; //GPIO native mode for GPP_H9 : params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08; //GPIO native mode for GPP_H8 : > board specific settings hardcoded?! Yeah, unfortunately EHL does not have UPD setting to bypass GPIO settings in FSP :( which means that some gpio will be overwritten in FSP even it is set in coreboot. I think EHL is the last project to have this flaw, so i did not come out with another full solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 12 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 15:16:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by Aamir Bohra (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Felix Held. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 9: (2 comments) File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/f21c47b0_90cb5ce5 PS9, Line 187: extra tab. https://review.coreboot.org/c/coreboot/+/60968/comment/9b265d11_bd2e3458 PS9, Line 210: extra tab. -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 9 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 15:06:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by Aamir Bohra (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Felix Held. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 9: (4 comments) File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/5f8f7577_2f3433d8 PS5, Line 33: default n can be dropped I believe, default in n. File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/af8554dc_e1c32d06 PS9, Line 34: help depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2? https://review.coreboot.org/c/coreboot/+/60968/comment/d22ab7f0_44279d6c PS9, Line 35: item config File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/4ef1e108_3536c022 PS9, Line 96: #define FUSE_STATUS_NOT_ALLOWED 0x09 : #define FUSE_STATUS_FUSING_ERR 0x0a : #define FUSE_STATUS_BOOT_DONE 0x0b can be moved up. -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 9 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 14:54:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Nico Huber, Sridhar Siricilla, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/3ffe5451_41c6c7aa PS2, Line 666: is_cse_fw_update_enabled > >So, if I read it correctly there is no restriction while reading OEM sections prior or post FSI. hence, why we would like to introduce a Kconfig to guard the read operation which would eventually get drop during FSI. Any owner for ensuring the same across program ? > > I don't see any benefit running this code since it is not useful once RO is locked. Hence, I want to guard the code and remove it before FSI. As I have highlighted earlier adding Kconfig is always costly plus its maintenance effort, who will maintain this addition and deletion, plus pulling that CL into upstream chromium etc. etc.. If there is no restriction (which I read is none), do you know about any time penalty if we wish to have this OEM section read unconditionally? > > >I could sense there are some underlying assumption which is not documented anything, either please raise a bug or write a .md file to clear out those assumptions. > > There are no assumptions or hidden things in this regard, I will update commit message with more information. Here are assumption which is not documented 1. Using OEM section for storing SoC debug information. which ideally can be managed using a soft-strap under debug strap. 2. Default value for bit-field, example: `1` is disable and `0` is enable or vice versa, 3. Any restriction this OEM region read need to be discarded in in FSI image. if yes, what is the boot time impact. 4. Comment suggests that, there are plan to add more configuration using OEM region and added a library. But what those configuration are not very clear just reading the commit msg. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 14:52:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2022