coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/i2c/designware/dw_i2c: add missing types.h include
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61508 ) Change subject: drivers/i2c/designware/dw_i2c: add missing types.h include ...................................................................... drivers/i2c/designware/dw_i2c: add missing types.h include This will provide the definitions for size_t, uint32_t and uintptr_t. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icda8d458565bf981545d720d612cbdace04bedd4 --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/61508/1 diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index a6498fb..1f7433e 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -8,6 +8,7 @@ #include <device/i2c_simple.h> #include <string.h> #include <timer.h> +#include <types.h> #include "dw_i2c.h" /* Use a ~10ms timeout for various operations */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icda8d458565bf981545d720d612cbdace04bedd4 Gerrit-Change-Number: 61508 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/aa6d1636_5828800e PS2, Line 666: is_cse_fw_update_enabled > > >So, if I read it correctly there is no restriction while reading OEM sections prior or post FSI. […] >As I have highlighted earlier adding Kconfig is always costly plus its maintenance effort, who will maintain this addition and deletion, plus pulling that CL into upstream chromium etc. etc.. Valid concern! Let's come back on this once proposal is ready. Ok? >1. Using OEM section for storing SoC debug information. which ideally can be managed using a soft-strap under debug strap. Soft strap is not advisable as this visible for other programs(Windows). Having the debug capability part of OEM Section, it gives more flexibility to coreboot to add/remove any functionality. >2. Default value for bit-field, example: `1` is disable and `0` is enable or vice versa, No plan to use bit fields. Each feature gets 1 byte slot in the OEM section. Value "1" is for invert the predetermined coreboot/SoC feature, for other values (0xff or any), no action. >3. Any restriction this OEM region read need to be discarded in in FSI image. if yes, what is the boot time impact. Hmm, I don't see any penalty >4.Comment suggests that, there are plan to add more configuration using OEM region and added a library. But what those configuration are not very clear just reading the commit msg. I will share the proposal (if you are willing to share your experience here) once it is ready. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 17:04:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add the fw SPL to amdfw.cfg
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Bao Zheng, Zheng Bao. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61445 ) Change subject: mb/google/guybrush: Add the fw SPL to amdfw.cfg ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg: https://review.coreboot.org/c/coreboot/+/61445/comment/6524d7c6_a37c6c0e PS1, Line 27: TypeId0x55_SplTable_Prod_CZN_Chrome Has this been pushed upstream yet? Who generated the binary, why is the chromeos specific? -- To view, visit https://review.coreboot.org/c/coreboot/+/61445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268a92c9916b261fbc899ebb72f75f7a3f12c441 Gerrit-Change-Number: 61445 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Mon, 31 Jan 2022 17:00:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add the fw SPL to fw.cfg
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Bao Zheng, Marshall Dawson, Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61425 ) Change subject: soc/amd/cezanne: Add the fw SPL to fw.cfg ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61425/comment/0bff53dd_dce57bfe PS2, Line 7: SPL What is the SPL table? Is this a Cezanne specific binary, or is it chromeos specific? -- To view, visit https://review.coreboot.org/c/coreboot/+/61425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0 Gerrit-Change-Number: 61425 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 16:59:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
by Cliff Huang (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Thejaswani Putta, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61353 to look at the new patch set (#5). Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control ...................................................................... soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control - Optional feature to provide mechanism to skip _OFF and _On execution. - It is used for the device to skip _OFF and _ON during device driver reload. - OFSK is used to skip _OFF Method at the end of device driver removal. - ONSK is used to skip _ON Method at the beginning of driver loading. - General flow use case: 1. Device driver is removed by 'rmmod' command. 2. Device _RST is called. _RST perform reset. 3. Device sets OFSK in _RST to skip the following _OFF invoked by OSPM. 4. OSPM invokes _OFF at the end of driver removal. 5. _OFF sees OFSK and skips current execution and clears OFSK so that _OFF will be executed normally next time. 6. _OFF sets ONSK to skip the following _ON invoked by OSPM. 7. Device driver is reloaded by 'insmod/modprobe' command. 8. OSPM invokes _ON at the beginning of driver loading. 9. _ON sees ONSK and skip current execution and clears ONSK so that _ON will be executed normally next time. - In normal case: When suspend, OSPM invokes _OFF. Since OFSK is not set, the device goes to deeper state as expected. When resume, OSPM invokes _ON. Sinc ONSK is not set, the device goes to active state as expected. - Generated changes: PowerResource (RTD3, 0x00, 0x0000) Name (ONSK, Zero) Name (OFSK, Zero) ... Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { ... } ElseIf ((ONSK == One)) { ONSK = Zero } } Method (_OFF, 0, Serialized) // _OFF: Power Off { If ((OFSK == Zero)) { ... } ElseIf ((OFSK == One)) { OFSK = Zero ONSK = One } } Test: Enable and verify OFSK and ONSK Name objects and the if-condition logic inside _OFF and _ON metheds is added. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/61353/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Gerrit-Change-Number: 61353 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Separate nipperkin and dewatt mem_parts_used table
by Raul Rangel (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Zheng Bao, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61452 ) Change subject: mb/google/guybrush: Separate nipperkin and dewatt mem_parts_used table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id30b596c2466902dfcc59dcc88dcaa00748a3949 Gerrit-Change-Number: 61452 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 16:45:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Add VT-x control via EEPROM
by Angel Pons (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Patrick Rudolph, Christian Walter. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61507 ) Change subject: mb/prodrive/hermes: Add VT-x control via EEPROM ...................................................................... mb/prodrive/hermes: Add VT-x control via EEPROM Introduce a new field in the board settings EEPROM region to control whether VT-x is to be enabled. Change-Id: If65c58dd6e5069dba1675ad875c7ac89e704350e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/hermes/eeprom.h M src/mainboard/prodrive/hermes/mainboard.c 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/61507/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h index 4b609df..f428a43 100644 --- a/src/mainboard/prodrive/hermes/eeprom.h +++ b/src/mainboard/prodrive/hermes/eeprom.h @@ -52,12 +52,13 @@ uint8_t front_panel_audio; uint8_t pxe_boot_capability; uint8_t pink_rear_vref; + uint8_t vtx_disabled; }; - uint8_t raw_settings[10]; + uint8_t raw_settings[11]; }; }; -_Static_assert(sizeof(struct eeprom_board_settings) == (10 + sizeof(uint32_t)), +_Static_assert(sizeof(struct eeprom_board_settings) == (11 + sizeof(uint32_t)), "struct eeprom_board_settings has invalid size!"); struct __packed eeprom_bmc_settings { diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index 6ca9613..2f0de61 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -240,6 +240,8 @@ /* Set Deep Sx */ config->deep_s5_enable_ac = board_cfg->deep_sx_enabled; config->deep_s5_enable_dc = board_cfg->deep_sx_enabled; + + config->disable_vmx = board_cfg->vtx_disabled; } if (check_signature(offsetof(struct eeprom_layout, supd), FSPS_UPD_SIGNATURE)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/61507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If65c58dd6e5069dba1675ad875c7ac89e704350e Gerrit-Change-Number: 61507 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Add `disable_vmx` devtree option
by Angel Pons (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61506 ) Change subject: soc/intel/cannonlake: Add `disable_vmx` devtree option ...................................................................... soc/intel/cannonlake: Add `disable_vmx` devtree option This option isn't meant to be assigned statically through devicetrees, but at runtime according to some config mechanism. It works in conjunction with the existing Kconfig option. Change-Id: Ia760be61466bc6a0ec187746e6e32537029512b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/61506/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 774b526..c7e71f6 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -448,6 +448,8 @@ /* Disable CPU Turbo in IA32_MISC_ENABLE */ bool cpu_turbo_disable; + + bool disable_vmx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 6af3e1a..10921a2 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -144,7 +144,8 @@ enable_turbo(); /* Enable Vmx */ - set_vmx_and_lock(); + set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !cfg->disable_vmx); + set_feature_ctrl_lock(); } static void per_cpu_smm_trigger(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/61506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia760be61466bc6a0ec187746e6e32537029512b4 Gerrit-Change-Number: 61506 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: Add `set_feature_ctrl_vmx_arg()`
by Angel Pons (Code Review) 01 Feb '22

01 Feb '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61505 ) Change subject: cpu/intel/common: Add `set_feature_ctrl_vmx_arg()` ...................................................................... cpu/intel/common: Add `set_feature_ctrl_vmx_arg()` Allow deciding whether to enable VMX through a function parameter. Used in a follow-up. Change-Id: I4f932de53207cd4e24cb4c67d20c60f708bfaa89 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/61505/1 diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 909f75a..ef0a5d9 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -8,6 +8,7 @@ void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); +void set_feature_ctrl_vmx_arg(bool enable); void set_feature_ctrl_lock(void); /* diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 765a174..0f40e4b 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -16,11 +16,10 @@ set_feature_ctrl_lock(); } -void set_feature_ctrl_vmx(void) +void set_feature_ctrl_vmx_arg(bool enable) { msr_t msr; uint32_t feature_flag; - int enable = CONFIG(ENABLE_VMX); feature_flag = cpu_get_feature_flags_ecx(); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -62,6 +61,12 @@ printk(BIOS_DEBUG, "VMX status: %s\n", enable ? "enabled" : "disabled"); } + +void set_feature_ctrl_vmx(void) +{ + set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX)); +} + void set_feature_ctrl_lock(void) { msr_t msr; -- To view, visit https://review.coreboot.org/c/coreboot/+/61505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f932de53207cd4e24cb4c67d20c60f708bfaa89 Gerrit-Change-Number: 61505 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 9: (6 comments) File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/b5ad4a76_8603733d PS5, Line 33: default n > can be dropped I believe, default in n. doesn't hurt to explicitly set default n. File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/a11d96c3_68be8900 PS9, Line 35: item > config Ack File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/88c301aa_df19d0da PS9, Line 96: #define FUSE_STATUS_NOT_ALLOWED 0x09 : #define FUSE_STATUS_FUSING_ERR 0x0a : #define FUSE_STATUS_BOOT_DONE 0x0b > these are used in fuse_status_to_string(). Ack https://review.coreboot.org/c/coreboot/+/60968/comment/3ce9a946_146de3d1 PS9, Line 96: #define FUSE_STATUS_NOT_ALLOWED 0x09 : #define FUSE_STATUS_FUSING_ERR 0x0a : #define FUSE_STATUS_BOOT_DONE 0x0b > these are used in fuse_status_to_string(). Ack https://review.coreboot.org/c/coreboot/+/60968/comment/e64e20d4_7a38fd54 PS9, Line 187: > extra space is added to split of printk line. Ack https://review.coreboot.org/c/coreboot/+/60968/comment/84b5d04f_429f7de5 PS9, Line 210: > extra space is added to split of printk line. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 9 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 16:39:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2022