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Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
soc/amd/common/block/psp: Add platform secure boot support
Add Platform Secure Boot (PSB) enablement via the PSP if it is not
already enabled. Upon receiving psb command, PSP will program PSB fuses
as long as BIOS signing key token is valid.
Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/Makefile.inc
A src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
5 files changed, 239 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60968/10
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Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
......................................................................
soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
Add L23 enter/exit, modPHY power gate, and source clock control methods.
DL23: method for L2/L3 entry.
L23D: method for L2/L3 exit.
PSD0: method for modPHY power gate.
SRCK: method for enabling/disable source clock.
These optional methods are to be used in the device ACPI to construct
flows with root port's power management functions.
Test:
Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f
---
M src/soc/intel/common/block/pcie/rtd3/chip.h
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
2 files changed, 105 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61352/5
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
......................................................................
soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
Add L23 enter/exit, modPHY power gate, and source clock control methods.
DL23: method for L2/L3 entry.
L23D: method for L2/L3 exit.
PSD0: method for modPHY power gate.
SRCK: method for enabling/disable source clock.
These optional methods are to be used in the device ACPI to construct
flows with root port's power management functions.
Test:
Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f
---
M src/soc/intel/common/block/pcie/rtd3/chip.h
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
2 files changed, 111 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61352/4
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61430 )
Change subject: soc/intel/common/cse: Make cse_disable_mei_devices a public function
......................................................................
Patch Set 4: Code-Review+2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
......................................................................
soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
- Optional feature to provide mechanism to skip _OFF and _On execution.
- It is used for the device to skip _OFF and _ON during device driver
reload.
- OFSK is used to skip _OFF Method at the end of device driver removal.
- ONSK is used to skip _ON Method at the beginning of driver loading.
- General flow use case:
1. Device driver is removed by 'rmmod' command.
2. Device _RST is called. _RST perform reset.
3. Device sets OFSK in _RST to skip the following _OFF invoked by OSPM.
4. OSPM invokes _OFF at the end of driver removal.
5. _OFF sees OFSK and skips current execution and clears OFSK so that
_OFF will be executed normally next time.
6. _OFF sets ONSK to skip the following _ON invoked by OSPM.
7. Device driver is reloaded by 'insmod/modprobe' command.
8. OSPM invokes _ON at the beginning of driver loading.
9. _ON sees ONSK and skip current execution and clears ONSK so that
_ON will be executed normally next time.
- In normal case:
When suspend, OSPM invokes _OFF. Since OFSK is not set, the device goes
to deeper state as expected.
When resume, OSPM invokes _ON. Sinc ONSK is not set, the device goes
to active state as expected.
- Generated changes:
PowerResource (RTD3, 0x00, 0x0000)
Name (ONSK, Zero)
Name (OFSK, Zero)
...
Method (_ON, 0, Serialized) // _ON_: Power On
{
If ((ONSK == Zero))
{
...
}
ElseIf ((ONSK == One))
{
ONSK = Zero
}
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
If ((OFSK == Zero))
{
...
}
ElseIf ((OFSK == One))
{
OFSK = Zero
ONSK = One
}
}
Test:
Enable and verify OFSK and ONSK Name objects and the if-condition logic
inside _OFF and _ON metheds is added.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/61353/4
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Change subject: mb/google/brya: Allow mainboard to lock `FPMCU_*` GPIO PADs
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
same comment in above CL :p
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Change subject: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This pin is restrict and consist, maybe be just in baseboard is enough?
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Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
......................................................................
Patch Set 1: Code-Review+1
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61474 )
Change subject: nb/intel/gm45/raminit.c: Fix indent for 'if' statement
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61474/comment/8d34be75_1c0410e7
PS2, Line 7: Fix
As per our coding guidelines? https://doc.coreboot.org/contributing/coding_style.html#breaking-long-lines…
› Statements longer than 96 columns will be broken into sensible chunks, unless exceeding 96 columns significantly increases readability and does not hide information. Descendants are always substantially shorter than the parent and are placed substantially to the right.
Note the "and are placed substantially to the right" part.
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