Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60721 )
Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/60721/comment/9f5131bb_f89f10a1
PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot.
> > > So it's just about hiding the interface, right? If so, we should name the […]
Hmm, Why not keep HECI in the name? DISABLE_HECI or HIDE_HECI
would be very clear to me. It could still say CSE in the prompt, e.g.
"Disable CSE interface (HECI)".
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60264 )
Change subject: mb/starlabs/labtop: Enable I2C4
......................................................................
mb/starlabs/labtop: Enable I2C4
Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be
enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from
configuring anything regarding I2C4 (e.g. GPIOs).
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Andy Pont <andy.pont(a)sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
Andy Pont: Looks good to me, but someone else must approve
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
index 35c2010..2e001c6 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -28,6 +28,7 @@
# Serial I/O
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
}"
register "SerialIoUartMode" = "{
@@ -165,7 +166,7 @@
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
end
- device pci 19.0 off end # I2C4
+ device pci 19.0 on end # I2C4
device pci 19.1 off end # I2C5
device pci 19.2 on end # UART #2
device pci 1c.0 off end # PCI Express Port 1
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60056 )
Change subject: nb/intel/i945/raminit.c: Set "integrated_graphics" as bool
......................................................................
nb/intel/i945/raminit.c: Set "integrated_graphics" as bool
"integrated_graphics" is already used as a "bool" at line #2128.
So set it as "bool".
Change-Id: Ic5286e691c312e8e44bbbd8e782fdfd4a13cb60f
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60056
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 03419ca..566d3e7 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2121,7 +2121,7 @@
{
u16 reg16;
u32 reg32;
- int integrated_graphics = 1;
+ bool integrated_graphics = true;
int i;
if (!(pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)))
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