coreboot-gerrit January 2022

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Change in coreboot[master]: soc/intel/common/cse: Add config to disable CSE at pre-boot
by Subrata Banik (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60721 ) Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/60721/comment/93c3b604_d5307b1b PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot. > Hmm, Why not keep HECI in the name? DISABLE_HECI or HIDE_HECI The only problem that I'm trying to avoid by not calling it "Heci" alone is that, there are multiple Heci devices so, DISABLE_HECI might sounds like we are providing API to make all heci devices disable. device pci 16.0 alias heci1 off end device pci 16.1 alias heci2 off end device pci 16.4 alias heci3 off end device pci 16.5 alias heci4 off end Otherwise we might need to say DISABLE/HIDE_HECI1 ? to specify its CSE/Heci1 alone. WDYT? > would be very clear to me. It could still say CSE in the prompt, e.g. > "Disable CSE interface (HECI)". Sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/60721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Gerrit-Change-Number: 60721 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 12:29:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Add option to change Boot Menu key
by Sean Rhodes (Code Review) 04 Jan '22

04 Jan '22

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60643 ) Change subject: payloads/tianocore: Add option to change Boot Menu key ...................................................................... Abandoned Created in a different way -- To view, visit https://review.coreboot.org/c/coreboot/+/60643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41df3e15aa73be41fb9836fe6e202319b02a3ffb Gerrit-Change-Number: 60643 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Martin Roth - Personal <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: payloads/tianocore: Add option to use F7 as Boot Manager key
by Sean Rhodes (Code Review) 04 Jan '22

04 Jan '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60761 ) Change subject: payloads/tianocore: Add option to use F7 as Boot Manager key ...................................................................... payloads/tianocore: Add option to use F7 as Boot Manager key The coreboot version of Tianocore maps Escape to the boot menu. This is problematic for many Linux distributions that use GRUB, as this also maps Escape to access it's menu. This option can be used to specific an F-Key to replace Escape Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ided23e82161488768aa3b7d54ab17e9c922d6d11 --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/60761/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index ade22b5..e5c76bf 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -148,6 +148,7 @@ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \ + CONFIG_TIANOCORE_BOOT_MANAGER_F7=$(CONFIG_TIANOCORE_BOOT_MANAGER_F7) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 1291122..bbc3788 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -116,6 +116,13 @@ bool "Enable Secure Boot Support" default y +config TIANOCORE_BOOT_MANAGER_F7 + bool "Use F7 key for Boot Manager" + default n + help + Use F7 as the hot-key to access the Boot Manager. This replaces + the default key of Esc, which can conflict with GRUB. + endif if TIANOCORE_COREBOOTPAYLOAD diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index e54b739..3aadf8e 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -46,6 +46,9 @@ 4G=-D ABOVE_4G_MEMORY=FALSE endif +ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_F7),y) +KEY=-D BOOT_MANAGER_F7=TRUE +endif ifeq ($(CONFIG_TIANOCORE_SECUREBOOT),y) SB=-D SECURE_BOOT_ENABLE=TRUE -- To view, visit https://review.coreboot.org/c/coreboot/+/60761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ided23e82161488768aa3b7d54ab17e9c922d6d11 Gerrit-Change-Number: 60761 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Add config to disable CSE at pre-boot
by Nico Huber (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60721 ) Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/60721/comment/9f5131bb_f89f10a1 PS2, Line 13: This config decides the state of CSE/Heci1 device at the end of boot. > > > So it's just about hiding the interface, right? If so, we should name the […] Hmm, Why not keep HECI in the name? DISABLE_HECI or HIDE_HECI would be very clear to me. It could still say CSE in the prompt, e.g. "Disable CSE interface (HECI)". -- To view, visit https://review.coreboot.org/c/coreboot/+/60721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Gerrit-Change-Number: 60721 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 12:19:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Modify DPTF setting for taeko
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60400 ) Change subject: mb/google/brya/var/taeko: Modify DPTF setting for taeko ...................................................................... mb/google/brya/var/taeko: Modify DPTF setting for taeko The new settings from the thermal team improve performance mainly with respect to fan control settings. BRANCH=None BUG=b:212210824 TEST=Built and tested on taeko board Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I2d5c9b6dff87a2e8897d74f3be89c965db22fe16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60400 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 2 files changed, 36 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 8a45385..7900172 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -142,31 +142,31 @@ [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } }, [2] = { .target = DPTF_TEMP_SENSOR_2, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } }, [3] = { .target = DPTF_TEMP_SENSOR_3, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } } }" @@ -192,7 +192,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 3000, - .max_power = 12000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, @@ -219,11 +219,11 @@ [0] = { 100, 6000, 220, 2200, }, [1] = { 92, 5500, 180, 1800, }, [2] = { 85, 5000, 145, 1450, }, - [3] = { 74, 4620, 115, 1150, }, - [4] = { 60, 4290, 90, 900, }, - [5] = { 45, 3980, 55, 550, }, - [6] = { 35, 3170, 30, 300, }, - [7] = { 30, 2640, 15, 150, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, [8] = { 10, 800, 10, 100, }, [9] = { 0, 0, 0, 50, } }" diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index b82e9de..6356661 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -138,31 +138,31 @@ [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } }, [2] = { .target = DPTF_TEMP_SENSOR_2, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } }, [3] = { .target = DPTF_TEMP_SENSOR_3, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } } }" @@ -188,7 +188,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 3000, - .max_power = 12000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, @@ -215,11 +215,11 @@ [0] = { 100, 6000, 220, 2200, }, [1] = { 92, 5500, 180, 1800, }, [2] = { 85, 5000, 145, 1450, }, - [3] = { 74, 4620, 115, 1150, }, - [4] = { 60, 4290, 90, 900, }, - [5] = { 45, 3980, 55, 550, }, - [6] = { 35, 3170, 30, 300, }, - [7] = { 30, 2640, 15, 150, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, [8] = { 10, 800, 10, 100, }, [9] = { 0, 0, 0, 50, } }" 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5c9b6dff87a2e8897d74f3be89c965db22fe16 Gerrit-Change-Number: 60400 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next build
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60330 ) Change subject: mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next build ...................................................................... mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next build Taeko is going to exchange i2c port for touchscreen and cr50. BUG=b:211911780 TEST=build pass Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60330 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/brya/variants/taeko/overridetree.cb 3 files changed, 34 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b000baf..ea4498a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -87,7 +87,7 @@ default 0x1 if BOARD_GOOGLE_REDRIX default 0x3 if BOARD_GOOGLE_REDRIX4ES default 0x1 if BOARD_GOOGLE_KANO - default 0x3 if BOARD_GOOGLE_TAEKO + default 0x1 if BOARD_GOOGLE_TAEKO default 0x3 if BOARD_GOOGLE_TAEKO4ES default 0x1 if BOARD_GOOGLE_FELWINTER default 0x3 if BOARD_GOOGLE_ANAHERA diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index aa778fc..a390604 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -140,10 +140,6 @@ static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -163,6 +159,10 @@ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index b82e9de..8a45385 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -79,11 +79,11 @@ #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | HPS | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C2 | HPS | + #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -91,7 +91,11 @@ .speed = I2C_SPEED_FAST, }, .i2c[1] = { + .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -272,6 +276,28 @@ end end device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c2 on + chip drivers/i2c/generic + register "hid" = ""GOOG0020"" + register "desc" = ""Chrome OS HPS"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL + # HPS uses I2C addresses 0x30 and 0x51. + # The address we provide here is not significant because + # neither coreboot nor Linux have a driver for HPS, + # it's only used from userspace. + device i2c 30 on + probe HPS HPS_PRESENT + end + end + end + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -312,28 +338,6 @@ device i2c 10 on end end end - device ref i2c2 on - chip drivers/i2c/generic - register "hid" = ""GOOG0020"" - register "desc" = ""Chrome OS HPS"" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL - # HPS uses I2C addresses 0x30 and 0x51. - # The address we provide here is not significant because - # neither coreboot nor Linux have a driver for HPS, - # it's only used from userspace. - device i2c 30 on - probe HPS HPS_PRESENT - end - end - end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/60330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d Gerrit-Change-Number: 60330 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: Set vGPIO reset type
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60334 ) Change subject: mb/google/brya/var/kano: Set vGPIO reset type ...................................................................... mb/google/brya/var/kano: Set vGPIO reset type Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207527331 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60334 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/gpio.c 1 file changed, 20 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index d77abea..e8c9032 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -139,26 +139,26 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* CPU PCIe VGPIO for PEG60 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; static const struct pad_config romstage_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b Gerrit-Change-Number: 60334 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/anahera: Add new memory support
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60411 ) Change subject: mb/google/brya/anahera: Add new memory support ...................................................................... mb/google/brya/anahera: Add new memory support Add the new memory support: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL Hynix H54G56CYRBX247 Samsung K4UBE3D4AB-MGCL BUG=b:212328327 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ib08a1348333accdbb7551ef428d8d130b621dd9f Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60411 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/memory/Makefile.inc M src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt M src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc M src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt 6 files changed, 24 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc b/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc index 68aa2f0..f8e3e62 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt index dcc5ba3..7b3a5e7 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -14,3 +14,7 @@ MT53E2G32D4NQ-046 WT:A 4 (0100) MT53E512M32D1NP-046 WT:B 1 (0001) MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) diff --git a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt index 71bd5fd..ca83c7f 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt @@ -8,3 +8,7 @@ MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc index 68aa2f0..6b9265e 100644 --- a/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt index dcc5ba3..2836162 100644 --- a/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -14,3 +14,7 @@ MT53E2G32D4NQ-046 WT:A 4 (0100) MT53E512M32D1NP-046 WT:B 1 (0001) MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt index 71bd5fd..ca83c7f 100644 --- a/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt @@ -8,3 +8,7 @@ MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/60411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08a1348333accdbb7551ef428d8d130b621dd9f Gerrit-Change-Number: 60411 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/redrix: Add new memory support
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60410 ) Change subject: mb/google/brya/var/redrix: Add new memory support ...................................................................... mb/google/brya/var/redrix: Add new memory support Add the new memory support: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL Hynix H54G56CYRBX247 Samsung K4UBE3D4AB-MGCL BUG=b:212330664 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I32491f86813c8e6566774d4b3d7d82295f906bd3 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60410 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/memory/Makefile.inc M src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt M src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc M src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt 6 files changed, 24 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc index 8590598..c023416 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt index 296634a..0349a4d 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -14,3 +14,7 @@ MT53E2G32D4NQ-046 WT:A 4 (0100) MT53E512M32D1NP-046 WT:B 1 (0001) MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) diff --git a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt index 71bd5fd..ca83c7f 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt @@ -8,3 +8,7 @@ MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc index 8590598..f9f2e5e 100644 --- a/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt index 296634a..61cb7fd 100644 --- a/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -14,3 +14,7 @@ MT53E2G32D4NQ-046 WT:A 4 (0100) MT53E512M32D1NP-046 WT:B 1 (0001) MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt index 71bd5fd..ca83c7f 100644 --- a/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt @@ -8,3 +8,7 @@ MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/60410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32491f86813c8e6566774d4b3d7d82295f906bd3 Gerrit-Change-Number: 60410 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/vell: update overridetree for DP
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60251 ) Change subject: mb/google/brya/var/vell: update overridetree for DP ...................................................................... mb/google/brya/var/vell: update overridetree for DP update override devicetree for type-c display based on schematics BUG=b:209489126 TEST=emerge-brya coreboot Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Change-Id: Icd2f5de38df0eb89fb92ea2abe25851c0d6ec53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60251 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 38 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 4f5da7f..825b305 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -46,9 +46,8 @@ #| | for TPM communication | #| I2C5 | Trackpad | #+-------------------+---------------------------+ - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 + # I2C Port Config register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -246,6 +245,8 @@ chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] device pnp 0c09.0 on end end end @@ -258,9 +259,19 @@ device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port3 as usb3_port - device generic 1 alias conn1 on end + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port4 as usb3_port + device generic 3 alias conn3 on end end end end @@ -275,11 +286,23 @@ device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "desc" = ""USB3 Type-C Port C1 (MlB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(3, 1)" device ref tcss_usb3_port3 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref tcss_usb3_port4 on end + end end end end @@ -293,11 +316,11 @@ device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port2 on end - end + end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" @@ -310,36 +333,17 @@ device ref usb2_port4 on end end chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port6 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (DB)"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb2_port9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port10 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (DB)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb3_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" - device ref usb3_port3 on end - end - chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port4 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/60251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd2f5de38df0eb89fb92ea2abe25851c0d6ec53f Gerrit-Change-Number: 60251 Gerrit-PatchSet: 10 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2022