coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: device: Add support for PCIe Resizable BARs
by Nico Huber (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 ) Change subject: device: Add support for PCIe Resizable BARs ...................................................................... Patch Set 2: (1 comment) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/61215/comment/2ade4eea_0afc30c0 PS2, Line 324: ctrl0 > can we rename this to rebar_ctrl_reg or ctrl_reg. When I read `reg` I assume it's describing the register, e.g. its offset, and not its content. > > Unable to understand why we have '0' here. See comment above and loop below, it's the first of many such register values and needs to be the first to work. -- To view, visit https://review.coreboot.org/c/coreboot/+/61215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Gerrit-Change-Number: 61215 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jan 2022 13:15:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/cpu: update CPUID
by Fred Reitberger (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61087 ) Change subject: soc/amd/sabrina/cpu: update CPUID ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e02e3491fb90941c767058986da876bdf7ca1d Gerrit-Change-Number: 61087 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Jan 2022 12:34:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_skl: disable HECI PCI device
by Paul Menzel (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Matt DeVillier, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61408 ) Change subject: mb/purism/librem_skl: disable HECI PCI device ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61408/comment/22ff4533_75e4cfa5 PS2, Line 9: As all librem_skl devices ship with the ME disabled via : HAP bit and ME firmware "neutralized" via me_cleaner, : the HECI1 PCI device should be marked off/disabled to : ensure that heci_init()/heci_reset() will not cause : a 15s timeout delay when booting. Please reflow for 72 characters per line. https://review.coreboot.org/c/coreboot/+/61408/comment/221a12e3_339e1835 PS2, Line 14: What commit introduced the regression? -- To view, visit https://review.coreboot.org/c/coreboot/+/61408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f Gerrit-Change-Number: 61408 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jan 2022 12:08:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/{drivers,soc}: Fix some code indents
by Paul Menzel (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Patrick Rudolph, HAOUAS Elyes. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61413 ) Change subject: src/{drivers,soc}: Fix some code indents ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff Gerrit-Change-Number: 61413 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 27 Jan 2022 12:04:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/external: Add more option related to SeaBIOS and GRUB2
by Paul Menzel (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Bill XIE, Martin Roth, Stefan Reinauer, Iru Cai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60640 ) Change subject: payloads/external: Add more option related to SeaBIOS and GRUB2 ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie681fa231abfe4a8f1e4510b3c17957550a9d2f8 Gerrit-Change-Number: 60640 Gerrit-PatchSet: 11 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jan 2022 12:03:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable SATA
by Paul Menzel (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61414 ) Change subject: mb/siemens/mc_ehl2: Disable SATA ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61414/comment/b9af3c33_ddc398c8 PS1, Line 10: mainboard. Maybe mention, that this board is still in development, and not “released” yet? -- To view, visit https://review.coreboot.org/c/coreboot/+/61414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf088ce4c907e207f6f5d11b8bf5556fe2c90d6 Gerrit-Change-Number: 61414 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 27 Jan 2022 12:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_d...
by Subrata Banik (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61331 ) Change subject: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61331/comment/320231b3_c4865690 PS6, Line 7: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree try to reflow this within 72 char in a line -- To view, visit https://review.coreboot.org/c/coreboot/+/61331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Gerrit-Change-Number: 61331 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Jan 2022 11:44:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_d...
by Subrata Banik (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61331 ) Change subject: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Gerrit-Change-Number: 61331 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Jan 2022 11:43:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: Add support for PCIe Resizable BARs
by Subrata Banik (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 ) Change subject: device: Add support for PCIe Resizable BARs ...................................................................... Patch Set 2: Code-Review+1 (5 comments) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/61215/comment/b9cc0656_b163bab0 PS2, Line 656: For instance, if a device requests : 30 bits of address space (1 GiB), but this field is set to 29, then : the device will only be allocated 29 bits worth of address space (512 : MiB). what will be the case when device may request for 28 bits address space (256MB) and default is set to 29 (512MB)? I believe it won't upgrade the bar instead allocate the BAR that device has requested. File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/61215/comment/f2132642_0c1f30e9 PS2, Line 324: ctrl0 can we rename this to rebar_ctrl_reg or ctrl_reg. Unable to understand why we have '0' here. https://review.coreboot.org/c/coreboot/+/61215/comment/f21c4d5d_8d7c62b8 PS2, Line 324: const uint32_t ctrl0 = pci_read_config32( : dev, offset + PCI_REBAR_CTRL_OFFSET); nit: I believe it can fit even in single line? https://review.coreboot.org/c/coreboot/+/61215/comment/1fedcf76_86e7d176 PS2, Line 330: ctrl regbar_cap_reg ? File src/include/device/pci_def.h: https://review.coreboot.org/c/coreboot/+/61215/comment/1bf22a10_b2af2144 PS2, Line 535: 0xe0 for easy understanding nit: (BIT 7 | BIT 6 | BIT 5) -- To view, visit https://review.coreboot.org/c/coreboot/+/61215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Gerrit-Change-Number: 61215 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jan 2022 11:40:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_d...
by EricR Lai (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61331 ) Change subject: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Gerrit-Change-Number: 61331 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Jan 2022 11:37:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2022