Attention is currently required from: Ravi kumar, mturney mturney.
Sudheer Amrabadi has uploaded a new patch set (#12) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/59556 )
Change subject: mb/google/herobrine: Add senor support QUP FW for I2C and SPI
......................................................................
mb/google/herobrine: Add senor support QUP FW for I2C and SPI
Add senor board to QUP FW load for: APPS I2C, ESIM SPI & fingerprint SPI.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I6fdd09bb437547e6d12eb60c4b2917d2a3074618
---
M src/mainboard/google/herobrine/mainboard.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/59556/12
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Gerrit-Change-Number: 59556
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Attention is currently required from: Ravi kumar.
Sudheer Amrabadi has uploaded a new patch set (#20) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/58545 )
Change subject: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot.
......................................................................
sc7280: Add Modem region to avoid modem cleanup in Secboot reboot.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: T Michael Turney <quic_mturney(a)quicinc.com>
Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95
---
M src/soc/qualcomm/common/include/soc/symbols_common.h
M src/soc/qualcomm/sc7280/Makefile.inc
A src/soc/qualcomm/sc7280/carve_out.c
M src/soc/qualcomm/sc7280/memlayout.ld
M src/soc/qualcomm/sc7280/soc.c
5 files changed, 31 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58545/20
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Change subject: amdfwtool: remove duplicates
......................................................................
Patch Set 1: Code-Review+1
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61327 )
Change subject: mb/google/dedede/var/metaknight: Set core display clock to 172.8 MHz
......................................................................
mb/google/dedede/var/metaknight: Set core display clock to 172.8 MHz
When using the default initial core display clock frequency, Metaknight
has a rare stability issue where the startup of Chrome OS in secure mode
may hang. Slowing the initial core display clock frequency down to
172.8 MHz as per Intel recommendation avoids this problem.
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for metaknight.
BUG=None
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/metaknight/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Ren Kuo: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index bb4762f..06da2d4 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -69,6 +69,9 @@
.tdp_pl2_override = 12,
}"
+ # Core Display Clock Frequency selection
+ register "cd_clock" = "CD_CLOCK_172_8_MHZ"
+
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
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Gerrit-MessageType: merged