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ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 )
Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
Patch Set 8:
(1 comment)
File src/soc/amd/common/block/psp/psb.c:
https://review.coreboot.org/c/coreboot/+/60968/comment/e434a616_8394b4a3
PS7, Line 220: if (psb_enable() == CB_ERR) {
> braces {} are not necessary for single statement blocks
Please fix.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Aamir Bohra, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60968
to look at the new patch set (#8).
Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
soc/amd/common/block/psp: Add platform secure boot support
Add Platform Secure Boot (PSB) enablement via the PSP if it is not
already enabled. Upon receiving psb command, PSP will program PSB fuses
as long as BIOS signing key token is valid.
Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/Makefile.inc
A src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
5 files changed, 241 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60968/8
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 )
Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15:
> Sridhar, would you mind adding an SSDT dump of CPPC to the bug, thanks!
Since SSDT dump of CPPC is huge, I will create a bug and add the SSDT dump of CPPC to it.
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61133 )
Change subject: soc/mediatek/mt8186: Support DRAM fast calibration using blob
......................................................................
Patch Set 24: Code-Review+1
(1 comment)
Patchset:
PS24:
Any suggestion for this patch?
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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61098 )
Change subject: soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL bits
......................................................................
Patch Set 5: Code-Review+1
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HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61423 )
Change subject: lib/spd_cache.c: Drop comparison to {true, false}
......................................................................
lib/spd_cache.c: Drop comparison to {true, false}
Change-Id: I0ef8c0159c99606aad537fd5e14d3c74e32651d8
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/lib/spd_cache.c
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61423/1
diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c
index be36141..44830a8 100644
--- a/src/lib/spd_cache.c
+++ b/src/lib/spd_cache.c
@@ -154,21 +154,21 @@
bool dimm_present_in_cache;
bool dimm_changed = false;
/* Check if the dimm is the same with last system boot. */
- for (i = 0; i < SC_SPD_NUMS && dimm_changed == false; i++) {
+ for (i = 0; i < SC_SPD_NUMS && !dimm_changed; i++) {
/* Return true if any error happened here. */
if (get_spd_sn(blk->addr_map[i], &sn) == CB_ERR)
return true;
dimm_present_in_cache = get_cached_dimm_present(spd_cache, i);
/* Dimm is not present now. */
if (sn == 0xffffffff) {
- if (dimm_present_in_cache == false)
+ if (!dimm_present_in_cache)
printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is not present\n", i);
else {
printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d lost\n", i);
dimm_changed = true;
}
} else { /* Dimm is present now. */
- if (dimm_present_in_cache == true) {
+ if (dimm_present_in_cache) {
if (memcmp(&sn, spd_cache + SC_SPD_OFFSET(i) + DDR4_SPD_SN_OFF,
SPD_SN_LEN) == 0)
printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is the same\n",
@@ -195,7 +195,7 @@
/* Find the first present SPD */
for (i = 0; i < SC_SPD_NUMS; i++)
- if (get_cached_dimm_present(spd_cache, i) == true)
+ if (get_cached_dimm_present(spd_cache, i))
break;
if (i == SC_SPD_NUMS) {
@@ -211,7 +211,7 @@
blk->len = SPD_PAGE_LEN;
for (i = 0; i < SC_SPD_NUMS; i++)
- if (get_cached_dimm_present(spd_cache, i) == true)
+ if (get_cached_dimm_present(spd_cache, i))
blk->spd_array[i] = spd_cache + SC_SPD_OFFSET(i);
else
blk->spd_array[i] = NULL;
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61414 )
Change subject: mb/siemens/mc_ehl2: Disable SATA
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61414/comment/595a48ae_c5a9b2c8
PS1, Line 10: mainboard.
> Maybe mention, that this board is still in development, and not “released” yet?
You are right. This should be mentioned.
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61414
to look at the new patch set (#2).
Change subject: mb/siemens/mc_ehl2: Disable SATA
......................................................................
mb/siemens/mc_ehl2: Disable SATA
With latest hardware revision SATA interface is no longer used on this
mainboard. The mainboard is still in development and not yet released
and for this reason there may still be adjustments.
Change-Id: Icbf088ce4c907e207f6f5d11b8bf5556fe2c90d6
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 1 insertion(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/61414/2
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