coreboot-gerrit January 2022

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Change in coreboot[master]: soc/intel/common/cse: Drop CSE library usage in bootblock
by Subrata Banik (Code Review) 27 Jan '22

27 Jan '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61382 ) Change subject: soc/intel/common/cse: Drop CSE library usage in bootblock ...................................................................... soc/intel/common/cse: Drop CSE library usage in bootblock This patch drops the CSE common code block from getting compiled in bootblock without any SoC code using heci communication so early in the boot flow. BUG=none TEST=Able to build brya, purism/librem_skl without any compilation issue. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib4d221c6f19b60aeaf64696e64d0c4209dbf14e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61382 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/cse/Makefile.inc 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 3f4c4d6..0e5dcda 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c -- To view, visit https://review.coreboot.org/c/coreboot/+/61382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4d221c6f19b60aeaf64696e64d0c4209dbf14e7 Gerrit-Change-Number: 61382 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: move heci_init() from bootblock to romstage
by Subrata Banik (Code Review) 27 Jan '22

27 Jan '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61378 ) Change subject: soc/intel/skylake: move heci_init() from bootblock to romstage ...................................................................... soc/intel/skylake: move heci_init() from bootblock to romstage Aligns with all other soc/intel/common platforms calling heci_init(). Test: build/boot Purism Librem 13v2 Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/romstage/romstage.c 2 files changed, 3 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 1685e43..ec60cab 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> -#include <intelblocks/cse.h> #include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> @@ -141,8 +140,5 @@ enable_rtc_upper_bank(); - /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); - gspi_early_bar_init(); } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 30f65ea..7e891b1 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -4,6 +4,7 @@ #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> +#include <intelblocks/cse.h> #include <intelblocks/pmclib.h> #include <intelblocks/smbus.h> #include <memory_info.h> @@ -127,6 +128,8 @@ systemagent_early_init(); /* Program SMBus base address and enable it */ smbus_common_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); ps = pmc_get_power_state(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); -- To view, visit https://review.coreboot.org/c/coreboot/+/61378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20 Gerrit-Change-Number: 61378 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC
by Krishna P Bhat D (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Subrata Banik, Kangheui Won, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61106 ) Change subject: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/alderlake/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/61106/comment/62ea8bef_f3f2d40f PS9, Line 9: #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) > This is already added in CB:61172 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Gerrit-Change-Number: 61106 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Jan 2022 10:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC
by Krishna P Bhat D (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Subrata Banik, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Krishna P Bhat D, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Reka Norman, Usha P, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61106 to look at the new patch set (#10). Change subject: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC ...................................................................... soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO IRQ routing information. GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups. GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO communities 5-0 respectively. BUG=b:213535859 Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/include/soc/gpio_defs.h M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 4 files changed, 301 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/61106/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/61106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Gerrit-Change-Number: 61106 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Rizwan Qureshi (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Arthur Heymans, Nico Huber, Subrata Banik, Paul Menzel, ravindr1, Sridhar Siricilla, Michael Niewöhner, Patrick Rudolph. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 15: Code-Review+2 (1 comment) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59359/comment/64fd141b_a2ef1fa3 PS15, Line 108: 0 > This is expected to be 0. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 15 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ravindr1 <ravindra(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ravindr1 <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Jan 2022 09:41:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/mipi_camera: Increase max power ops count to 6
by Subrata Banik (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61146 ) Change subject: driver/intel/mipi_camera: Increase max power ops count to 6 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80 Gerrit-Change-Number: 61146 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Jan 2022 08:43:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create crota variant
by Terry Chen (Code Review) 27 Jan '22

27 Jan '22

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61416 ) Change subject: mb/google/brya: Create crota variant ...................................................................... mb/google/brya: Create crota variant Create the crota variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:215443524 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CROTA Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ic8f1a0bde286d5d014dfdf87c2a417ca6ff8b3a3 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/crota/include/variant/ec.h A src/mainboard/google/brya/variants/crota/include/variant/gpio.h A src/mainboard/google/brya/variants/crota/memory/Makefile.inc A src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/crota/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/61416/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 7de078a..5af1f4b 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -152,6 +152,7 @@ default "Agah" if BOARD_GOOGLE_AGAH default "Volmar" if BOARD_GOOGLE_VOLMAR default "Banshee" if BOARD_GOOGLE_BANSHEE + default "Crota" if BOARD_GOOGLE_CROTA config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -176,6 +177,7 @@ default "agah" if BOARD_GOOGLE_AGAH default "volmar" if BOARD_GOOGLE_VOLMAR default "banshee" if BOARD_GOOGLE_BANSHEE + default "crota" if BOARD_GOOGLE_CROTA config VBOOT select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 26c90da..123c25b 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -155,3 +155,7 @@ bool "-> Banshee" select BOARD_GOOGLE_BASEBOARD_BRYA select MEMORY_SODIMM + +config BOARD_GOOGLE_CROTA + bool "-> Crota" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/crota/include/variant/ec.h b/src/mainboard/google/brya/variants/crota/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/crota/include/variant/gpio.h b/src/mainboard/google/brya/variants/crota/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/crota/memory/Makefile.inc b/src/mainboard/google/brya/variants/crota/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/61416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8f1a0bde286d5d014dfdf87c2a417ca6ff8b3a3 Gerrit-Change-Number: 61416 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/intel/mipi_camera: Increase max power ops count to 6
by Varshit B Pandya (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Tim Wawrzynczak, Patrick Rudolph. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61146 ) Change subject: driver/intel/mipi_camera: Increase max power ops count to 6 ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61146/comment/03b6f8f6_b6aa786e PS4, Line 9: Current max count for camera power ops is 5 which is not sufficient, > Please make that a sentence by itself (dot/period and no comma). […] So if you see the patch on top of it explains in detail why we need it, its because of hardware limitation, two devices sharing the same reset PCH GPIO https://review.coreboot.org/c/coreboot/+/61146/comment/0df06fe2_eef1540d PS4, Line 10: if we increase the ops by 1 in current variants the compiler : will throw error for intel mipi camera driver > 1. Please add a dot/period at the end of sentences. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80 Gerrit-Change-Number: 61146 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 Jan 2022 08:36:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/mipi_camera: Increase max power ops count to 6
by Varshit B Pandya (Code Review) 27 Jan '22

27 Jan '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Sugnan Prabhu S, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Sugnan Prabhu S, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61146 to look at the new patch set (#6). Change subject: driver/intel/mipi_camera: Increase max power ops count to 6 ...................................................................... driver/intel/mipi_camera: Increase max power ops count to 6 Current max count for camera power ops is 5 which is not sufficient. If we increase the ops by 1 in current variants the compiler will not throw error for intel mipi camera driver. Hence increase current max count for camera power ops to 6 from 5. BUG=b:214665783 TEST=Build and boot to OS Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80 --- M src/drivers/intel/mipi_camera/chip.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/61146/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80 Gerrit-Change-Number: 61146 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCIe RPs
by Mario Scheithauer (Code Review) 27 Jan '22

27 Jan '22

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61415 ) Change subject: mb/siemens/mc_ehl2: Disable PCIe RPs ...................................................................... mb/siemens/mc_ehl2: Disable PCIe RPs With latest hardware revision only PCIe RP2 and RP7 are used on this mainboard. Change-Id: I7702c2b9058dde1c819cb1df8a68fd602f5997da Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 4 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/61415/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4982384..438419a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -43,18 +43,15 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" @@ -64,17 +61,11 @@ register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports - register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports - register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" - register "PcieRpLtrDisable[2]" = "true" - register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[6]" = "true" # Storage (SDCARD/EMMC) related UPDs @@ -156,10 +147,7 @@ device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.2 on end # RP3 (pcie0 single VC) - device pci 1c.4 on end # RP5 (pcie1 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE) -- To view, visit https://review.coreboot.org/c/coreboot/+/61415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7702c2b9058dde1c819cb1df8a68fd602f5997da Gerrit-Change-Number: 61415 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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