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Change subject: mb/google/zork/var/vilboz: Add new memory K4AAG165WB-BCWE
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Hi Google,
Would you help to merge the CL?
Then we can work on it in ToT after it gets upstreamed.
Thank you.
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Change subject: mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61373/comment/6b9f66b6_15c2c6d1
PS2, Line 16: 0x0010 MICRON MT40A1G16KD-062E:E
> It should be a binary instead of hex.
Done.
Sorry, my mistake.
Thanks.
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Hello build bot (Jenkins), Kangheui Won, Isaac Lee, Bhanu Prakash Maiya,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61373
to look at the new patch set (#3).
Change subject: mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
......................................................................
mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
Add supported memory parts in "mem_parts_used.txt" and generate
the SPD ID 0x04 for the parts.
Shuboz memory table as follow:
value Vendor Part number
0000 MICRON MT40A512M16TB-062E:J
0001 HYNIX H5AN8G6NCJR-XNC
0010 MICRON MT40A1G16KD-062E:E
0011 SAMSUNG K4AAG165WA-BCWE
0100 MICRON MT40A512M16TB-062E:R
BUG=b:216571906
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com>
Change-Id: Ib0100456457adabed6fd6615e0873de2cf9acb98
---
M src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
M src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
M src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
3 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/61373/3
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Change subject: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree
......................................................................
Patch Set 5: -Code-Review
(1 comment)
File src/soc/intel/common/block/pcie/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/61331/comment/ef0ac2ae_d0a862e2
PS5, Line 133: &&
> use "or" here? if the groups is NULL, the second check will crash.
Valid point.
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Change subject: mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61373/comment/cdab839b_609e7d27
PS2, Line 16: 0x0010 MICRON MT40A1G16KD-062E:E
It should be a binary instead of hex.
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Change subject: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree
......................................................................
Patch Set 5:
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File src/soc/intel/common/block/pcie/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/61331/comment/a83f15dc_801c0811
PS5, Line 133: &&
use "or" here? if the groups is NULL, the second check will crash.
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Change subject: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree
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Patch Set 5: Code-Review+2
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Change subject: mb/google/brya: Fill in gpio.h for nissa baseboard
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Change subject: mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
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