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Change subject: mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCM
......................................................................
mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCM
Drawcia's MIPI camera sensor and VCM both share the same reset GPIO
from the PCH. The current power sequence does not take this into
account, and this leads to an unbalanced ref count of the reset GPIO,
which can cause one or the other of the devices to reset unexpectedly.
This patch corrects that by explicitly sequencing the reset GPIO for
both devices, which the builtin refcounting of this driver will
automatically handle.
BUG=b:214665783
TEST=Build, boot to OS and check VCM once camera stream off
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89
---
M src/mainboard/google/dedede/variants/drawcia/overridetree.cb
1 file changed, 10 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/61147/5
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Change subject: driver/intel/mipi_camera: Increase max power ops count to 6
......................................................................
driver/intel/mipi_camera: Increase max power ops count to 6
Current max count for camera power ops is 5 which is not sufficient.
If we increase the ops by 1 in current variants the compiler
will throw error for intel mipi camera driver.
Hence increase current max count for camera power ops to 6 from 5.
BUG=b:214665783
TEST=Build and boot to OS
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80
---
M src/drivers/intel/mipi_camera/chip.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/61146/5
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61401 )
Change subject: soc/intel/appololake: Allow to configure SATA ALPM via devicetree
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61401/comment/bb39d375_af4a5ea5
PS1, Line 7: Add ability to config SATA via UPD
> Allow to configure SATA ALPM via devicetree
Done
https://review.coreboot.org/c/coreboot/+/61401/comment/f250bb38_eccec4d1
PS1, Line 9: config
> devicetree
Done
https://review.coreboot.org/c/coreboot/+/61401/comment/0f475e7e_66589c62
PS1, Line 11: disturbing under a
> unwanted, for example for a real-time system
Done
https://review.coreboot.org/c/coreboot/+/61401/comment/d4595753_a06ef18d
PS1, Line 12: ALPM must be able to be disable
> allow to disable ALPM using the devicetree
Done
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61413 )
Change subject: src/{drivers,soc}: Fix some code indents
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/appololake: Allow to configure SATA ALPM via devicetree
......................................................................
soc/intel/appololake: Allow to configure SATA ALPM via devicetree
Add a devicetree option to disable SATA Aggressive Link Power
Management. ALPM is a method of saving power. The corresponding FSP-S
UPD parameter is enabled by default. It may be that this feature is
unwanted, for example for a real-time system. Therefore, allow to
disable ALPM using the devicetree.
Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/61401/2
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Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61331 )
Change subject: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/pcie/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/61331/comment/86744f2e_2793d22a
PS5, Line 133: &&
> Valid point.
Ack
Thank you for pointing out Eric.
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Change subject: mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
......................................................................
Patch Set 3: Code-Review+2
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