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Hello build bot (Jenkins), Reka Norman, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61126
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
......................................................................
soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
Alder Lake N has eMMC storage device. Add PCR Port ID for it.
Reference: Alder Lake N platform EDS Doc# 645548.
Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/soc/intel/alderlake/include/soc/pcr_ids.h
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/61126/4
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61130
to look at the new patch set (#9).
Change subject: mb/intel/adlrvp: Enable eMMC device for ADL-N RVP
......................................................................
mb/intel/adlrvp: Enable eMMC device for ADL-N RVP
Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder
Lake N RVP from devicetree.
Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/mainboard/intel/adlrvp/devicetree_n.cb
M src/mainboard/intel/adlrvp/gpio_n.c
2 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/61130/9
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John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61283 )
Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> Just question here. Before the FSP-S, p2sb is unhidden and FSP-S will hide that. […]
There is no scenario that coreboot tries to hide p2sb before FSP-S. It seems fine.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58869 )
Change subject: drivers/intel/fsp2_0/include/fsp: fix fsp_header
......................................................................
Patch Set 8:
(4 comments)
File src/drivers/intel/fsp2_0/header_display.c:
https://review.coreboot.org/c/coreboot/+/58869/comment/e47c200f_060c169b
PS8, Line 28: %s
this probably needs to be %.8s; see my comment below
https://review.coreboot.org/c/coreboot/+/58869/comment/5c46a005_f20941d0
PS8, Line 29: hdr->image_id
this is no longer a zero terminated c string, so you need to adjust the printk format specifier to only use 8 characters
File src/drivers/intel/fsp2_0/include/fsp/info_header.h:
https://review.coreboot.org/c/coreboot/+/58869/comment/6a4898f0_b53a083d
PS8, Line 29: api_entry_num
this should probably be res2. a change from the fsp info header block from the fsp 1.1 to fsp 2.0 was "Renamed ApiEntryNum to Reserved2" and this header file is specific to fsp2.x
File src/drivers/intel/fsp2_0/util.c:
https://review.coreboot.org/c/coreboot/+/58869/comment/442482fc_41a532d3
PS8, Line 54: if (!looks_like_fsp_header(raw_hdr))
i'd pass a struct fsp_header to looks_like_fsp_header instead of the raw binary to avoid using hard-coded offsets there too. that's something for a separate follow-up patch though
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Change subject: mb/google/volteer/var/collis: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Please ensure this gets cherry-picked to the FW branch after it lands in the chromium tree
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Change subject: mb/google/volteer/var/collis: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60415/comment/a060eabf_5e362251
PS8, Line 18: TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Can you also add
`BRANCH=volteer`
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Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Patchset:
PS7:
Just question here. Before the FSP-S, p2sb is unhidden and FSP-S will hide that. So if before FSP-S, it hidden by coreboot. Will that causes some issue?
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