Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. ......................................................................
mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,282 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1
diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..f56a2a2 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig new file mode 100644 index 0000000..4b3c127 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig @@ -0,0 +1,68 @@ +if BOARD_ACER_VN7_572G + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_SKYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform has no way to see POST codes so disable them by default. + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "Aspire V Nitro" + +config MAINBOARD_PART_NUMBER + string + default "Aspire VN7-572G" + +config MAINBOARD_DIR + string + default "acer/aspire_vn7_572g" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,1916" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name new file mode 100644 index 0000000..b881680 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_VN7_572G + bool "Aspire VN7-572G" diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl new file mode 100644 index 0000000..2eed489 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl @@ -0,0 +1,328 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (EMBA, 0xFE800000) + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID + + Name (_GPE, 0x50) // _GPE: General Purpose Events + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + }) + OperationRegion (ECO1, SystemIO, 0x62, One) + Field (ECO1, ByteAcc, Lock, Preserve) + { + PX62, 8 + } + + OperationRegion (ECO2, SystemIO, 0x66, One) + Field (ECO2, ByteAcc, Lock, Preserve) + { + PX66, 8 + } + + OperationRegion (ECMB, SystemMemory, EMBA, 0x0200) + OperationRegion (RAM, EmbeddedControl, Zero, 0xFF) + Field (RAM, ByteAcc, Lock, Preserve) + { + CMDB, 8, + Offset (0x06), + CMD2, 8, + CMD1, 8, + CMD0, 8, + Offset (0x0A), + , 1, /* Reserved */ + , 1, /* Reserved */ + Offset (0x10), + EQEN, 1, + , 1, /* Reserved */ + Offset (0x4E), + ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */ + Offset (0x51), + , 3, /* Reserved */ + TPEN, 1, + Offset (0x52), + WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */ + BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */ + EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */ + , 3, /* Reserved */ + RFEX, 1, + Offset (0x57), + , 7, /* Reserved */ + AHKB, 1, + AHKE, 8, + Offset (0x5C), + Offset (0x5D), + Offset (0x70), + , 1, /* Reserved */ + KLID, 1, /* LID? */ + , 3, /* Reserved */ + KACS, 1, /* AC power? */ + Offset (0x71), + WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */ + BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */ + , 3, /* Reserved */ + ISS3, 1, + ISS4, 1, + ISS5, 1, + Offset (0x74), + , 2, /* Reserved */ + , 1, /* Reserved */ + TPEX, 1, + Offset (0x75), + BLST, 1, + LMIB, 1, + Offset (0x76), + ECSS, 4, + EOSS, 4 + } + + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + /* Initialize AC power state */ + Store (KACS, \PWRS) + + /* Initialize LID switch state */ + Store (KLID, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + /* Battery Information Event */ + Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* AC event */ + Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (ADP1, 0x80) // Status Change + } + + /* Lid event */ + Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (LID0, 0x80) // Status Change + } + + /* Battery Information Event */ + Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* Battery Status Event */ + Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x80) // Status Change + } + + Method (ECWK, 1, NotSerialized) + { + EQEN = One + Notify (BAT0, 0x81) // Information Change + If (((Arg0 == 0x03) || (Arg0 == 0x04))) + { + Notify (SLPB, 0x02) // Device Wake + } + } + + Name (B0ST, Zero) + Field (ECMB, ByteAcc, Lock, Preserve) + { + Offset (0x08), + MB0S, 8 + } + + OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF) + Field (MBB0, ByteAcc, Lock, Preserve) + { + MBRC, 16, + MBFC, 16, + MBPE, 16, + MBAC, 16, + MBVO, 16, + , 15, + MBCM, 1, + MBCU, 16, + MBTV, 16 + } + + Method (GBIF, 3, NotSerialized) + { + If (Arg2) + { + Arg1 [One] = 0xFFFFFFFF + Arg1 [0x02] = 0xFFFFFFFF + Arg1 [0x04] = 0xFFFFFFFF + Arg1 [0x05] = Zero + Arg1 [0x06] = Zero + } + + Return (Arg1) + } + + Method (GBST, 4, NotSerialized) + { + Local0 = Zero + + If ((Arg1 & One)) + { + Local1 = MBAC /* _SB_.PCI0.LPCB.EC0_.MBAC */ + Local2 = MBRC /* _SB_.PCI0.LPCB.EC0_.MBRC */ + If (ACST) + { + If ((Arg1 & 0x20)) + { + Local2 = MBFC /* _SB_.PCI0.LPCB.EC0_.MBFC */ + } + } + + Local3 = MBVO /* _SB_.PCI0.LPCB.EC0_.MBVO */ + If ((Local1 >= 0x8000)) + { + If ((Local0 & One)) + { + Local1 = (0x00010000 - Local1) + } + Else + { + Local1 = Zero + } + } + + If (Arg2) + { + Local1 *= Local3 + Divide (Local1, 0x03E8, Local1) + } + } + Else + { + Local0 = Zero + Local1 = 0xFFFFFFFF + Local2 = 0xFFFFFFFF + Local3 = 0xFFFFFFFF + } + + Arg3 [Zero] = Local0 + Arg3 [One] = Local1 + Arg3 [0x02] = Local2 + Arg3 [0x03] = Local3 + Return (Arg3) + } + + Name (ACST, One) + Device (ADP1) + { + Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID + Name (_PCL, Package () { _SB }) // _PCL: Power Consumer List + Method (_PSR) // _PSR: Power Source + { + Return (\PWRS) + } + Method (_STA) // _STA: Status + { + Return (0x0F) + } + } + + Device (BAT0) + { + Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* _SB_ */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B0ST) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (B0IP, Package (0x0D) + { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0x00000000, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "100", /* 0x0a: Serial Number */ + "Lion", /* 0x0b: Battery Type */ + 0x00000000 /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Local6 = B0ST /* _SB_.PCI0.LPCB.EC0_.B0ST */ + While ((Local6)) + { + Local1 = MB0S /* _SB_.PCI0.LPCB.EC0_.MB0S */ + If ((Local1 & 0x08)) + { + Local6 = Zero + } + } + + Return (GBIF (Zero, B0IP, Local6)) + } + + Name (B0SP, Package (0x04) + { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Local0 = (DerefOf (B0IP [Zero]) ^ One) + Return (GBST (Zero, MB0S, Local0, B0SP)) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl new file mode 100644 index 0000000..e145a2b --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero) +Field (SANV, AnyAcc, Lock, Preserve) +{ + BRTL, 8 +} + +Scope (_SB.PCI0) +{ + Device (GFX0) + { + Name (_ADR, 0x00020000) // _ADR: Address + + Device (DD1F) + { + Method (_ADR, 0, Serialized) // _ADR: Address + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels + { + Return (Package (0x0C) + { + 0x50, + 0x32, + 0x0A, + 0x14, + 0x1E, + 0x28, + 0x32, + 0x3C, + 0x46, + 0x50, + 0x5A, + 0x64 + }) + } + + Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method + { + If (((Arg0 >= Zero) && (Arg0 <= 0x64))) + { + BRTL = Arg0 + } + } + + Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current + { + Return (BRTL) /* \BRTL */ + } + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl new file mode 100644 index 0000000..90e75f2 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB) +{ + Device (LID0) /* Lid Device */ + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + + Method (_LID) // _LID: Lid Status + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt new file mode 100644 index 0000000..f16707e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: Aspire VN7-572G +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb new file mode 100644 index 0000000..f38b0b8 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -0,0 +1,218 @@ +chip soc/intel/skylake + + # Disable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x60-0x66 + register "gen1_dec" = "0x00000061" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "0" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "SaGv" = "0" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root Ports 1, 9 and 10 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + +# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. +# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl new file mode 100644 index 0000000..c9bcb7d --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h new file mode 100644 index 0000000..4d98da1 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */ +_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */ +_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */ +_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */ +_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */ +_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */ +_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */ +_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */ +_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */ +_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */ +_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */ +_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */ +_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */ +_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */ +_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */ +_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */ +_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */ +_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */ +_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */ +_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */ +_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */ +_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */ +_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */ +_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */ +_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */ +_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */ +_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */ +_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */ +_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */ +_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */ +_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */ +_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */ +_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */ +_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */ +_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */ + +_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */ +_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */ +_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */ +_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */ +_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */ +_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */ +_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */ +_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */ +_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */ +_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */ +_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */ +_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */ +_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */ +_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */ +_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */ +_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */ +_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */ +_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */ +_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */ +_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */ +_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */ +_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */ +_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */ +_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */ +_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */ +_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */ +}; + +#endif + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c new file mode 100644 index 0000000..8cd5f97 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Purism SPC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0x10251037, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */ + AZALIA_SUBVENDOR(0x0, 0x10251037), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90172120), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40000000), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x02211030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c new file mode 100644 index 0000000..86ef5af --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +}
Hello Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#2).
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
mb/acer/aspire_vn7_572g: Adds support for an Acer laptop
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,282 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
Patch Set 2:
Oh, hi there! I see you got to upload the change we talked about on the mailing list, nice :D
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
Patch Set 2:
(4 comments)
Just a little clean up..
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 11: select MAINBOARD_USES_FSP2_0 Not necessary, since it is selected by the SOC.
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 13: select MAINBOARD_HAS_LPC_TPM According to some Google results, it should have a TPM2. So please also select `MAINBOARD_HAS_TPM2`.
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 22: default "Acer" Not necessary, since this is set by the upper Kconfig file "src/mainboard/acer/Kconfig".
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 36: config DEVICETREE : string : default "devicetree.cb" Not necessary, since this is already the default.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#3).
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
mb/acer/aspire_vn7_572g: Adds support for an Acer laptop
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,275 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/3
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
Patch Set 3:
(1 comment)
Thanks. I've fixed the others, but it appears that FSP 2.0 must be defined if it is being used.
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 11: select MAINBOARD_USES_FSP2_0
Not necessary, since it is selected by the SOC.
I was advised that FSP 2.0 supported Skylake. While I haven't personally tested this (I've been unable to flash any new images for a little while, but I'm working on it), without this line it defaults to using FSP 1.1.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#4).
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
mb/acer/aspire_vn7_572g: Adds support for an Acer laptop
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,275 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/4
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
Patch Set 4:
(4 comments)
Please make sure after solving issues to mark them as "Resolved".
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 11: select MAINBOARD_USES_FSP2_0
I was advised that FSP 2.0 supported Skylake. […]
You are right, sorry. I thought this would be the default for Skylake, but only if you select the Kaby Lake soc.
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 13: select MAINBOARD_HAS_LPC_TPM
According to some Google results, it should have a TPM2. So please also select `MAINBOARD_HAS_TPM2`.
Done
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 22: default "Acer"
Not necessary, since this is set by the upper Kconfig file "src/mainboard/acer/Kconfig".
Done
https://review.coreboot.org/c/coreboot/+/35523/2/src/mainboard/acer/aspire_v... PS2, Line 36: config DEVICETREE : string : default "devicetree.cb"
Not necessary, since this is already the default.
Done
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
Patch Set 4:
Oh, ok. I wasn't sure if anyone would disagree about the FSP 2.0 detail, but I'll make sure to do that in the future. Thanks.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG@7 PS4, Line 7: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop mb/acer: Add Acer Aspire VN7-572G
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG@7 PS4, Line 7: Adds Imperative mood: Add
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG@9 PS4, Line 9: Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. Please adhere to the line length limit of 75 characters.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#5).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,275 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/5
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#6).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,275 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/6
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG@7 PS4, Line 7: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop
mb/acer: Add Acer Aspire VN7-572G
Done
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG@7 PS4, Line 7: Adds
Imperative mood: Add
Very well
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG@9 PS4, Line 9: Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Please adhere to the line length limit of 75 characters.
Sorry. Is one newline sufficient?
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#7).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,277 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/7
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#8).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Internal audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other I2C values. These could be 0x51 and 0x53) -HDMI audio -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,277 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/8
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 8:
SPI flash console log: https://gist.github.com/benjamindoron/7d0b2d58ba65ac37c60f1ab6391d0ca0
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#9).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Internal audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -HDMI audio -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,277 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/9
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#10).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Internal audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -HDMI audio -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,302 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/10
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#11).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,302 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/11
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/11/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/35523/11/src/mainboard/acer/aspire_... PS11, Line 74: Assuming here that another "{double ,}function reset" would undo previous configuration
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#12).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,306 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/12
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#13).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/13
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 13:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 18: # GPE configuration How are these found? They look like GPIO tables, but I haven't found the dwords.
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 80: # VR Settings Configuration for 4 Domains OEM BIOS seems to literally disable VR config. Also guessing that it uses FSP 1.1, it has 5 domains.
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 150: # register "PcieRpEnable[6]" = "1" Port 7 is enabled in OEM BIOS. Is this perhaps NVMe?
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#14).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/14
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 14:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35523/14/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/14/src/mainboard/acer/aspire_... PS14, Line 51: config CPU_MICROCODE_CBFS_LEN Is this the length of one microcode or the whole blob? How likely is it to change in the future?
https://review.coreboot.org/c/coreboot/+/35523/14/src/mainboard/acer/aspire_... PS14, Line 59: config CBFS_SIZE Assuming that CBFS can be $flash_size - ($intel_descriptor + $intel_ME), this is now correct. (but isn't ME only 1.5MB, just padded out to 2MB?)
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#15).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore CorebootPayload) -Display (tried FSP GOP + VBT) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/15
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#16).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore (at least no logging is occurring) and SeaBIOS (halts after unexpected APIC exception) -Display (tried FSP GOP + VBT and OptionROM) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff (lspci devices aren't found and are disabled) -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/16
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#17).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore (at least no logging is occurring) and SeaBIOS master (halts after unexpected APIC exception) -Display (tried FSP GOP + VBT and OptionROM) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff (lspci devices aren't found and are disabled) -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/17
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 17:
Is it possible that Tiano isn't logging to CBMEM (and probably isn't finding Fedora's fallback shim loader) and SeaBIOS didn't work because I run a UEFI system (or because it's SeaBIOS, or SeaBIOS master)? That coreboot is loading the payload but that I have no way of seeing it?
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#18).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore (at least no logging is occurring) and SeaBIOS master (halts after unexpected APIC exception) -Display (tried FSP GOP + VBT as well as OptionROM) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff (lspci devices aren't found and are disabled) -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000 -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/18
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 18:
Console log (running Tiano): https://gist.github.com/benjamindoron/af2d29e7b19ba96e915c9ecd8793c2b4 Console log (running SeaBIOS): https://gist.github.com/benjamindoron/6bf3052a40b515f226a0cbbb7b33f4ac
They're the same build (different configuration, but same mainboard code), so it's just that halt (unexpected APIC exception) while starting SeaBIOS that's noteworthy.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#19).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore (at least no logging is occurring) and SeaBIOS master (halts after unexpected APIC exception) -Display (tried FSP GOP + VBT as well as OptionROM) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff (some lspci devices aren't found and are disabled) -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/19
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#20).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Adds initial, rudimentary support for Acer Aspire VN7-572G.
Works: -Some amount of booting -2/4 RAM slots
Assumed working: -Audio
Does not work: -Loading payload (tried Tianocore (at least no logging is occurring) and SeaBIOS master (halts after unexpected APIC exception) -Display (tried FSP GOP + VBT as well as OptionROM) -Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) -Some PCIe stuff (some lspci devices aren't found and are disabled) -TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) -Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/20
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 20:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@9 PS20, Line 9: Adds Add
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@12 PS20, Line 12: -Some amount of booting Please be more specific.
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@15 PS20, Line 15: Assumed working: Untested?
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@19 PS20, Line 19: Tianocore TianoCore
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@11 PS20, Line 11: Works: : -Some amount of booting : -2/4 RAM slots : : Assumed working: : -Audio : : Does not work: : -Loading payload (tried Tianocore (at least no logging is occurring) : and SeaBIOS master (halts after unexpected APIC exception) : -Display (tried FSP GOP + VBT as well as OptionROM) : -Remaining RAM slots (need other SPD addresses. : These could be 0x51 and 0x53) : -Some PCIe stuff (some lspci devices aren't found and are disabled) : -TPM ("tis_probe: No TPM device found" but : "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")? : : Unknown: : -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) : -Microcode update (FIT states a size of 0, update is skipped) Please add a space after the “bullet point”.
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@32 PS20, Line 32: One blank line is enough.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#21).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Some amount of booting - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Loading payload (tried TianoCore (at least no logging is occurring) and SeaBIOS master (halts after unexpected APIC exception) - Display (tried FSP GOP + VBT as well as OptionROM) - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some lspci devices aren't found and are disabled) - TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,309 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/21
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 21:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@9 PS20, Line 9: Adds
Add
Done
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@12 PS20, Line 12: -Some amount of booting
Please be more specific.
With TianoCore as the payload, the last line of the log is "jumping to bootcode at..." SeaBIOS halts with an "unexpected APIC exception." Regardless, I have no graphics.
I initially wrote that line when I figured that something ultimately stopped TianoCore from loading, but I don't actually know if it's meant to be logging. I tried SeaBIOS only because I know that it logs to CBMEM.
Now I'm trying to get graphics working so that I can see what it's doing. I've extracted a VBT from the vendor BIOS (4 KB) to try instead of the one I retrieved from in Linux (6 KB) and I'll build another image.
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@15 PS20, Line 15: Assumed working:
Untested?
I haven't successfully booted into an OS yet, so while the console log says that it loaded the verb tables, yes, it's untested.
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@19 PS20, Line 19: Tianocore
TianoCore
Done
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@11 PS20, Line 11: Works: : -Some amount of booting : -2/4 RAM slots : : Assumed working: : -Audio : : Does not work: : -Loading payload (tried Tianocore (at least no logging is occurring) : and SeaBIOS master (halts after unexpected APIC exception) : -Display (tried FSP GOP + VBT as well as OptionROM) : -Remaining RAM slots (need other SPD addresses. : These could be 0x51 and 0x53) : -Some PCIe stuff (some lspci devices aren't found and are disabled) : -TPM ("tis_probe: No TPM device found" but : "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")? : : Unknown: : -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) : -Microcode update (FIT states a size of 0, update is skipped)
Please add a space after the “bullet point”.
Done
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@32 PS20, Line 32:
One blank line is enough.
Done
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#22).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Some amount of booting - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Loading payload (tried TianoCore (at least no logging is occurring) and SeaBIOS master (halts after unexpected APIC exception) - Display (tried FSP GOP + VBT as well as OptionROM) - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some lspci devices aren't found and are disabled) - TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,341 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/22
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#23).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Some amount of booting - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Loading payload (tried TianoCore (at least no logging is occurring) and SeaBIOS master (halts after unexpected APIC exception) - Display (tried FSP GOP + VBT as well as OptionROM) - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some lspci devices aren't found and are disabled) - TPM ("tis_probe: No TPM device found" but "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")?
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/23
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#24).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting. Haven't gotten into an OS yet. Presently assuming that once display is working, selecting an OS should work - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Display's backlight works with FSP GOP + customised KBL VBT, display does not work at all with libgfxinit. - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled)
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/24
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 24:
(2 comments)
Just some random comments, I stumbled upon the libgfxinit+panel mention.
https://review.coreboot.org/c/coreboot/+/35523/24//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/24//COMMIT_MSG@21 PS24, Line 21: does not work at all with libgfxinit. I don't see any panel configuration in the devicetree[1]. The GOP does partial configuration based on the VBT, but doesn't set everything, AFAIK. Hence, I always advice to fill all applicable settings.
Um, just noticed the documentation doesn't mention the backlight PWM configuration. Which is most likely what is missing for libgfxinit support. Make sure to set `gpu_pch_backlight_pwm_hz` as well.
[1] https://doc.coreboot.org/gfx/display-panel.html
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default. Not that I personally use the option, but with this, one can't enable POST codes on the console anymore. Maybe a
config NO_POST default y
would serve better?
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 24:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/4//COMMIT_MSG@9 PS4, Line 9: Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Sorry. […]
I'll assume so, unless notified otherwise.
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default.
Not that I personally use the option, but with this, one can't enable POST […]
What do you mean? Do you mean that someone with this device wouldn't be able to use POST codes if they had a way of viewing them, or do you mean that this breaks it across the tree?
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#25).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting. Haven't gotten into an OS yet. Presently assuming that once display is working, selecting an OS should work - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Display's backlight works with FSP GOP + customised KBL VBT, display does not work at all with libgfxinit. - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/25
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default.
What do you mean? Do you mean that someone with this device wouldn't be able to use POST codes if th […]
There is an option to print the post codes to the console. That would not work anymore.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#26).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting. Haven't gotten into an OS yet. Presently assuming that once display is working, selecting an OS should work - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Display's backlight works with FSP GOP + customised KBL VBT, display does not work at all with libgfxinit. - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,356 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/26
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 26:
(1 comment)
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default.
There is an option to print the post codes to the console. That would not work anymore.
Done
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#27).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting. Haven't gotten into an OS yet. Presently assuming that once display is working, selecting an OS should work - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Display's backlight works with FSP GOP + customised KBL VBT, display does not work at all with libgfxinit. - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/27
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default.
Done
Jenkins complains that this would break other boards which use the board-specific method.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default.
Jenkins complains that this would break other boards which use the board-specific method.
I see. Although, this means those boards should be fixed anyway, if they block proper solutions elsewhere.
I'm also not sure if `config` is correct with the warning. At least an explicit `depends on y` in console/Kconfig fixes it, too. Shouldn't that be implied? Maybe not if the symbol was already declared with dependencies elsewhere.
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default.
I see. Although, this means those boards should be fixed […]
I've switched my copy to the "config NO_POST" method and I'll change it here after those boards get changed.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#28).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting. Haven't gotten into an OS yet. Presently assuming that once display is working, selecting an OS should work - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Display's backlight works with FSP GOP + customised KBL VBT, display does not work at all with libgfxinit. - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - ACPI - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/28
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#29).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting. Haven't gotten into an OS yet. Presently assuming that once display is working, selecting an OS should work - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Display's backlight works with FSP GOP + customised KBL VBT, display does not work at all with libgfxinit. - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - ACPI - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,367 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/29
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#30).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting. Haven't gotten into an OS yet. Presently assuming that once display is working, selecting an OS should work - 2/4 RAM slots
Assumed working: - Audio
Does not work: - Display's backlight works with FSP GOP + customised KBL VBT, display does not work at all with libgfxinit. - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - ACPI - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,367 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/30
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#31).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,367 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/31
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#32).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses. These could be 0x51 and 0x53) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,367 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/32
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#34).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,367 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/34
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#35).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 21 files changed, 1,943 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/35
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 35:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/35/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/35523/35/src/mainboard/acer/aspire_... PS35, Line 63: Zero, trailing whitespace
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#36).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 21 files changed, 1,943 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/36
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#38).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 21 files changed, 1,940 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/38
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 39:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@12 PS20, Line 12: -Some amount of booting
With TianoCore as the payload, the last line of the log is "jumping to bootcode at... […]
Done
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@15 PS20, Line 15: Assumed working:
I haven't successfully booted into an OS yet, so while the console log says that it loaded the verb […]
Done
https://review.coreboot.org/c/coreboot/+/35523/14/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/14/src/mainboard/acer/aspire_... PS14, Line 51: config CPU_MICROCODE_CBFS_LEN
Is this the length of one microcode or the whole blob? How likely is it to change in the future?
Apparently only necessary for FSP-T.
https://review.coreboot.org/c/coreboot/+/35523/14/src/mainboard/acer/aspire_... PS14, Line 59: config CBFS_SIZE
Assuming that CBFS can be $flash_size - ($intel_descriptor + $intel_ME), this is now correct. […]
Corrected now.
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/24/src/mainboard/acer/aspire_... PS24, Line 18: select NO_POST # This platform has no way to see POST codes so disable them by default.
I've switched my copy to the "config NO_POST" method and I'll change it here after those boards get […]
Done
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 80: # VR Settings Configuration for 4 Domains
OEM BIOS seems to literally disable VR config. Also guessing that it uses FSP 1.1, it has 5 domains.
VR config has now been set appropriately for SKL-U
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#40).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 21 files changed, 1,943 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/40
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 40:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/40//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/40//COMMIT_MSG@28 PS40, Line 28: - Display (with libgfxinit) Would be good to test
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 110: // ^^^GFX0.GLID (KLID) ?
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 42: // If (CondRefOf (_SB.TPM.PTS)) ?
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 71: register "SaGv" = "3" There should be an enum for SaGv values (not sure if Skylake has it)
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 50: // Chipset specific sleep states "common" isn't really "chipset specific", so maybe drop the comment?
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 34: /* Pin Complex (NID 0x12) */ Please remove these comments, they don't provide useful info
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#41).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 21 files changed, 1,917 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/41
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 41:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 110: // ^^^GFX0.GLID (KLID)
?
Vendor BIOS calls this method inside the graphics device, which I need to rewrite or remove. The method is commented out here so that it isn't lost until I can do this.
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 42: // If (CondRefOf (_SB.TPM.PTS))
?
Vendor BIOS calls the prepare-to-sleep method on the TPM's ACPI device. As I understand, coreboot generates the ACPI table for the TPM dynamically, this will either be removed or tagged as external.
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 50: // Chipset specific sleep states
"common" isn't really "chipset specific", so maybe drop the comment?
Done
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 34: /* Pin Complex (NID 0x12) */
Please remove these comments, they don't provide useful info
Done
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#42).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial, rudimentary support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Display (with FSP GOP + KBL VBT) - 2/4 RAM slots - Internal audio - Keyboard and touchpad (presuming that keyboard will only work in UEFI with an edit to UefiPayloadPkg definition file)
Does not work: - Headphone jack - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe - ACPI (battery and AC not recognised, lid not working)
Unknown: - Display (with libgfxinit) - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 21 files changed, 1,918 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/42
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#43).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - 2/4 RAM slots - Keyboard and touchpad (at this time, use CorebootPayload for UEFI support)
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 21 files changed, 1,918 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/43
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#44).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - 2/4 RAM slots - Keyboard and touchpad (at this time, use CorebootPayload for UEFI support)
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Remaining RAM slots (need other SPD addresses) - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,878 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/44
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 45: Code-Review+1
(8 comments)
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG@23 PS45, Line 23: ACPI You can dump the DSDT of the vendor firmware. For EC stuffs, that is usually the only way to make it work. For example, do you have a battery device? Even if not using Arch Linux, you can use this guide to dump and decompile the DSDT:
https://wiki.archlinux.org/index.php/DSDT#Recompiling_it_yourself
You don't need to recompile it. Rather, use the source as a reference to check things against.
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG@28 PS45, Line 28: - Remaining RAM slots (need other SPD addresses) How many RAM slots does this thing have?
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 110: // ^^^GFX0.GLID (KLID)
Vendor BIOS calls this method inside the graphics device, which I need to rewrite or remove. […]
Ack
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 42: // If (CondRefOf (_SB.TPM.PTS))
Vendor BIOS calls the prepare-to-sleep method on the TPM's ACPI device. […]
Ack
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 150: # register "PcieRpEnable[6]" = "1"
Port 7 is enabled in OEM BIOS. […]
NVMe should have x4 lanes. If it does, it might be it
https://review.coreboot.org/c/coreboot/+/35523/11/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/35523/11/src/mainboard/acer/aspire_... PS11, Line 74:
Assuming here that another "{double ,}function reset" would undo previous configuration
I think so. I'll mark this as resolved.
https://review.coreboot.org/c/coreboot/+/35523/45/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/35523/45/src/mainboard/acer/aspire_... PS45, Line 29: 0x10251037 No need to repeat the literal hex value in the comment
https://review.coreboot.org/c/coreboot/+/35523/45/src/mainboard/acer/aspire_... PS45, Line 38: 0x1A nit: use lowercase for these hex constants
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 45:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35523/40//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/40//COMMIT_MSG@28 PS40, Line 28: - Display (with libgfxinit)
Would be good to test
Done
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 71: register "SaGv" = "3"
There should be an enum for SaGv values (not sure if Skylake has it)
It does, so you should use `SaGv_Enabled`:
/* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. * 0 = Disabled * 1 = FixedLow * 2 = FixedHigh * 3 = Enabled */ enum { SaGv_Disabled, SaGv_FixedLow, SaGv_FixedHigh, SaGv_Enabled, } SaGv;
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 45:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG@23 PS45, Line 23: ACPI
You can dump the DSDT of the vendor firmware. […]
I've redone the ACPI table since the first, broken one, but haven't tested it yet. I had planned to test all this at once, but the display (mainly dGPU at this time) is still giving me trouble.
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG@28 PS45, Line 28: - Remaining RAM slots (need other SPD addresses)
How many RAM slots does this thing have?
The vendor firmware and dmidecode list 4, but the internet says that there are only 2.
I checked the datasheet just now, which also only lists 2. I'll remove this, but will fix it if I find evidence to the contrary.
(I've also realised now that the vendor firmware would have been written for many devices, so hidden information in the advanced settings might even be a lie, after a fashion. dmidecode cannot help with confirmation on this, because it receives information from the vendor firmware)
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 150: # register "PcieRpEnable[6]" = "1"
NVMe should have x4 lanes. […]
I enabled it in the list of PCI devices and it probably doesn't hurt to enable it in general. I'm just concerned that these ports need special clock values, etc, that I don't know yet.
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/40/src/mainboard/acer/aspire_... PS40, Line 71: register "SaGv" = "3"
It does, so you should use `SaGv_Enabled`: […]
Done
https://review.coreboot.org/c/coreboot/+/35523/45/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/35523/45/src/mainboard/acer/aspire_... PS45, Line 29: 0x10251037
No need to repeat the literal hex value in the comment
Done
https://review.coreboot.org/c/coreboot/+/35523/45/src/mainboard/acer/aspire_... PS45, Line 38: 0x1A
nit: use lowercase for these hex constants
Done
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#46).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,878 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/46
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#47).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,802 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/47
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#48).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,801 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/48
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#49).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,805 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/49
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#50).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,805 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/50
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#51).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/globalnvs.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 20 files changed, 2,232 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/51
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#52).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,089 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/52
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#53).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,147 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/53
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 53:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35523/53/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/53/src/mainboard/acer/aspire_... PS53, Line 31: static void gpu_reset(void) { open brace '{' following function definitions go on the next line
https://review.coreboot.org/c/coreboot/+/35523/53/src/mainboard/acer/aspire_... PS53, Line 48: while (! gpio_get(DGPU_PWROK)) { space prohibited after that '!' (ctx:BxW)
https://review.coreboot.org/c/coreboot/+/35523/53/src/mainboard/acer/aspire_... PS53, Line 69: static void mainboard_init(struct device *dev) { open brace '{' following function definitions go on the next line
https://review.coreboot.org/c/coreboot/+/35523/53/src/mainboard/acer/aspire_... PS53, Line 75: static void mainboard_enable(struct device *dev) { open brace '{' following function definitions go on the next line
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#54).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/54
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 54:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG@28 PS45, Line 28: - Remaining RAM slots (need other SPD addresses)
The vendor firmware and dmidecode list 4, but the internet says that there are only 2. […]
Um, RAM slots are a physical thing you can count. For example, a random board off the internets:
https://us.v-cdn.net/6029997/uploads/editor/2l/a82ghszhap9b.jpg
There's two slots, each can take a SO-DIMM. On laptops, there's usually only two SO-DIMM slots.
If there's onboard memory (memory-down), there's usually the equivalent of one or two DIMMs.
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 54:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG@28 PS45, Line 28: - Remaining RAM slots (need other SPD addresses)
Um, RAM slots are a physical thing you can count. For example, a random board off the internets: […]
I know. I added a second RAM stick to this laptop once.
I remember slightly doubting the vendor firmware/DMI tables when I saw how there didn't seem to be any space for two more slots underneath the visible ones. If the board in that image only has two, it would seem to confirm my doubts.
I was anyways going to trust the schematics over the firmware, but this is one more indicator to that effect. And that vendor firmware can be unreliable.
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... PS54, Line 33: gpio_get(DGPU_PRESENT) Schematics: "H: UMA, L: OPTIMUS" This check might need to be inverted.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 54:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/45//COMMIT_MSG@28 PS45, Line 28: - Remaining RAM slots (need other SPD addresses)
I know. I added a second RAM stick to this laptop once. […]
(the board in the image isn't your board, but if you only saw two slots then it's all good)
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... PS54, Line 33: gpio_get(DGPU_PRESENT)
Schematics: "H: UMA, L: OPTIMUS" […]
Oh, you managed to get the schematics?
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 54:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... PS54, Line 33: gpio_get(DGPU_PRESENT)
Oh, you managed to get the schematics?
I hope that there's no policy against using them, but yes.
Ah. I mentioned "datasheet" before, but I was referring to the same document.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#55).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,148 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/55
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#56).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/56
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#57).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to Switchable Graphics (matching vendor's configuration, enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys - Some PCIe stuff (some devices in lspci aren't found and are disabled) - M.2/NVMe
Unknown: - EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) - Microcode update (FIT states a size of 0, update is skipped)
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,158 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/57
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#58).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX (enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,158 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/58
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#59).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX (enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,158 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/59
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#61).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 30 using TianoCore - Memory - Keyboard and touchpad
Requires testing: - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX (enabling dGPU)) - with FSP GOP + KBL VBT - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,160 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/61
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#62).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,160 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/62
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62: Code-Review+1
Does SeaBIOS also work?
Let’s get this in, as the payload can be loaded.
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62:
Does SeaBIOS also work?
I haven't tested SeaBIOS lately because I've been trying to get my laptop working as is. Does the config have any significant differences? Months ago, it gave me some kind of APIC exception.
Let’s get this in, as the payload can be loaded.
Isn't that a little too early? The problem could be coreboot-related (I've had no luck with enabling the 8254 timer, but it could be something else).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 55: #config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID This can go away, I guess?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 155: Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF Have you figured out what these EC queries do? It would be nice to comment what they are about.
With Linux, you can add ASL "debug prints" and apply them with a DSDT override, all while using the vendor firmware. The idea to see what vendor firmware does with this.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 107: #| AC LoadLine | 10.3 mOhm | 2.4 mOhm | 3.1 mOhm | 3.1 mOhm | Out of curiosity, where do you get the loadline values from?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 46: // Mainboard specific Is it necessary to use two different files? If so, can any of them be renamed to, for example, `ec.asl` ?
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... PS54, Line 33: gpio_get(DGPU_PRESENT)
I hope that there's no policy against using them, but yes. […]
I haven't heard of any policy against wanting to do things properly :)
Personally, I strongly prefer using schematics. It is much better than guessing things.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: system76 hmmmmm
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 18: # GPE configuration
How are these found? They look like GPIO tables, but I haven't found the dwords.
I think you answered your own question?
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 55: #config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
This can go away, I guess?
Why? I didn't want to enable too much at once, but isn't it good to inform the OS of the hardware, so that it can apply quirks if it needs?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 155: Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
Have you figured out what these EC queries do? It would be nice to comment what they are about. […]
At the moment, I can hazard guesses based on which device is notified and by corroborating the values with other ACPI code. I can work on this, but it'll be easier once an OS will boot.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 107: #| AC LoadLine | 10.3 mOhm | 2.4 mOhm | 3.1 mOhm | 3.1 mOhm |
Out of curiosity, where do you get the loadline values from?
6th Generation Intel Processor for U/Y-Platforms Datasheet, Volume 1 of 2 (#332990)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: system76
hmmmmm
It is fairly generic code and I have modified it, mostly according to the schematics and what I've seen of Intel's SwitchableGraphics.
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 18: # GPE configuration
I think you answered your own question?
Yes, I suppose :)
Skylake laptops seem to use the same GPIO communities. These are correct.
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 150: # register "PcieRpEnable[6]" = "1"
I enabled it in the list of PCI devices and it probably doesn't hurt to enable it in general. […]
Port 7 actually backs SATA. Port 8 is NGFF.
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/54/src/mainboard/acer/aspire_... PS54, Line 33: gpio_get(DGPU_PRESENT)
I haven't heard of any policy against wanting to do things properly :) […]
Of course. No idea what I thought could possibly be an issue (their copyright couldn't prevent our use)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62: Code-Review+1
(13 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 55: #config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Why? I didn't want to enable too much at once, but isn't it good to inform the OS of the hardware, s […]
This symbol isn't used anywhere: https://github.com/coreboot/coreboot/search?q=MAINBOARD_PCI_SUBSYSTEM_VENDOR...
I know, it was used before, but it's now gone. Refer to the seven commits on GitHub search results
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 155: Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
At the moment, I can hazard guesses based on which device is notified and by corroborating the value […]
Well, you can apply ACPI overrides even when using the vendor BIOS: https://wiki.archlinux.org/index.php/DSDT
I used that to track down how special keys work on a Sony laptop.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 53: 0 This one should be enabled in order to use a SATA SSD.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 58: 2 Shouldn't this be 3 for SATA3 6Gbps speeds?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 107: #| AC LoadLine | 10.3 mOhm | 2.4 mOhm | 3.1 mOhm | 3.1 mOhm |
6th Generation Intel Processor for U/Y-Platforms Datasheet, Volume 1 of 2 (#332990)
Ack, thanks
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 202: register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth Missing `usb2_ports[5]` for the touch screen? (likely unused)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 204: register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD Also missing `usb2_ports[8]` for the "finger printer"
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 208: # register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port This and `usb3_ports[3]` seem to be used for USB Type-C
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 232: [PchSerialIoIndexUart2] = PchSerialIoDisabled, This could be enabled as a debug port. Maybe "SkipInit" ?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 240: device pci 01.0 on end # Dedicated Graphics Device I don't think SKL-U has such device. This is the PEG port on the SA (System Agent), and it is not present on U nor Y series chips.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 253: device pci 1c.0 on end # PCI Express Port 1 This is actually the dGPU root port. Would be nice to add a comment
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 26: DP1, Not used, the DP AUX channel is not available over HDMI (for obvious reasons)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: system76
It is fairly generic code and I have modified it, mostly according to the schematics and what I've s […]
Ack. I would update the prints however
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
PS62: This is a lot of code given the "unknown" state in the commit message. Is the status stale or is this untested, copied code? If the latter, please only add it once you could test it, and understood it (makes it easier to write readable code).
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 62:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: 0x7CE7D018 This looks like a very bad idea. AIUI, it's a physical DRAM address and could conflict with coreboot.
Hello Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#63).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,155 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/63
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 63:
(14 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 55: #config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
This symbol isn't used anywhere: https://github. […]
Ah, okay.
So we don't do this anymore?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 29: 0xFE800000 FIXME: This defines a hardcoded memory region.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: 0x7CE7D018
This looks like a very bad idea. AIUI, it's a physical DRAM address and […]
That does sound very bad. How should this be handled instead?
The named variable "EMBA" does the same for other opregions. Marking as such.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 53: 0
This one should be enabled in order to use a SATA SSD.
Done
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 58: 2
Shouldn't this be 3 for SATA3 6Gbps speeds?
I found an ATA error in dmesg once, even with the vendor BIOS. I thought I'd try this, in case limiting the speed fixes it, as it did for Purism's board. There isn't an error there now, though.
Removing this.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 170: x4 In the schematics, ports 1-4 are connected to PEG. Should these ports be enabled?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 202: register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
Missing `usb2_ports[5]` for the touch screen? (likely unused)
Device does not have a touchscreen.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 204: register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
Also missing `usb2_ports[8]` for the "finger printer"
Not present.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 208: # register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
This and `usb3_ports[3]` seem to be used for USB Type-C
There's only one Type-C port?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 232: [PchSerialIoIndexUart2] = PchSerialIoDisabled,
This could be enabled as a debug port. […]
Done
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 240: device pci 01.0 on end # Dedicated Graphics Device
I don't think SKL-U has such device. […]
You're right. Volume 2 of the datasheet for 6th gen platforms concurs. Is it sufficient to enable the root port? While coreboot doesn't remove Port 1 (dGPU), it doesn't locate anything behind it either[1], so something seems to be missing.
1. It may not be useful, but the log is here: https://gist.github.com/benjamindoron/37204d78c915d3fb7801462416d65c2d
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 253: device pci 1c.0 on end # PCI Express Port 1
This is actually the dGPU root port. […]
Very well.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 26: DP1,
Not used, the DP AUX channel is not available over HDMI (for obvious reasons)
Done
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: system76
Ack. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 63:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 58: 2
I found an ATA error in dmesg once, even with the vendor BIOS. […]
Ack. I wonder if the issue with the Purism Librem is due to lack of HSIO tuning or just bad design. There are HSIO tuning registers but they are publicly undocumented.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 170: x4
In the schematics, ports 1-4 are connected to PEG. […]
No, they should be left disabled. There's a difference between PCIe root port devices and PCIe lanes. The dGPU is using four PCIe lanes (1..4), but they are all grouped together in a single PCIe root port device.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 202: register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
Device does not have a touchscreen.
Not at all, or not on your model? Leaving it enabled does not cause any harm.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 204: register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
Not present.
See above
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 208: # register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
There's only one Type-C port?
USB Type-C uses two USB 3.0 lanes, though. Yes, I didn't know about that either.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 240: device pci 01.0 on end # Dedicated Graphics Device
You're right. Volume 2 of the datasheet for 6th gen platforms concurs. […]
Notice that, on line 371, coreboot says it could not find this device. That is, Bus:Dev.Fun 00:01.0 is missing. The GPU should be on a different bus, at 01:00.0
If the dGPU isn't present with coreboot, it is probably power gated because of Optimus.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 63:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/Kconfig:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 55: #config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Ah, okay. […]
On older platforms, it is done in the devicetree. I don't really bother much with subsystem IDs, though. Maybe I should.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 63:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 29: 0xFE800000
FIXME: This defines a hardcoded memory region.
Given the high location, this will be some hardware MMIO. Which may be chosen by the firmware.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: 0x7CE7D018
That does sound very bad. How should this be handled instead?
Depends on what the code tries to do, and to be honest, reading it seems like a reverse engineering effort. ACPI features are best added step by step, e.g. you miss battery status, add that, you want an Fn-key to work, add that etc. Copying vendor code (which I assume this is) is a sure way to waste time (unless one doesn't care and accepts to have 80% dead, unreadable code).
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#64).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,876 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/64
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 64:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 170: x4
No, they should be left disabled. […]
Okay, thanks. I see from FspmUpd.h ("Peg*" UPDs) that the FSP handles this automatically?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 202: register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
Not at all, or not on your model? Leaving it enabled does not cause any harm.
Fair point. Enabling.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 204: register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
See above
Done
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 208: # register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
USB Type-C uses two USB 3.0 lanes, though. Yes, I didn't know about that either.
Done
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 64:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/mbdefines.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 29: 0xFE800000
Given the high location, this will be some hardware MMIO. Which may be […]
Definitely the vendor firmware, or is this value universal? In any case, I'll have to work on this.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 34: 0x7CE7D018
That does sound very bad. How should this be handled instead? […]
I've fixed this by factoring it out and including some functionality from EC_ACPI. However, I haven't managed to implement everything I've removed and this remains untested.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 46: // Mainboard specific
Is it necessary to use two different files? If so, can any of them be renamed to, for example, `ec. […]
Were you referring to mbdefines.asl? If so, the remainder of that has since been refactored into dsdt.asl after including EC_ACPI.
This remains untested; I haven't managed to implement everything that I've removed.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#65).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,890 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/65
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 65: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/35523/65/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/65/src/mainboard/acer/aspire_... PS65, Line 674: /* WBEC: Calls SMI function 0x11 */ Those SMI functions are not there on coreboot, are they?
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 170: x4
Okay, thanks. I see from FspmUpd. […]
"Peg" usually refers to the PCIe lanes attached to the CPU, which do not exist on SKL-U
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 240: device pci 01.0 on end # Dedicated Graphics Device
Notice that, on line 371, coreboot says it could not find this device. That is, Bus:Dev.Fun 00:01. […]
Done
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 46: // Mainboard specific
Were you referring to mbdefines. […]
Right. The idea is to avoid having both "mbdefines" and "mainboard", as they sound a bit redundant.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#66).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,916 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/66
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 66:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35523/65/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/35523/65/src/mainboard/acer/aspire_... PS65, Line 674: /* WBEC: Calls SMI function 0x11 */
Those SMI functions are not there on coreboot, are they?
No. I also think think that my assumption that 0x10-0x12 mapped to 0x80-0x82 (EC_WRITE is 0x81) was incorrect. The vendor implements a generic handler which receives 0x80-0x82 as well as 0x10 (from "RBEC" method).
These are possibly generic EC SCI commands? The KB9012QF datasheet, page 169, lists SCI events 0x10 and 0x11 for FAN0 and FAN1, as well as 0x12 for SMBus events.
I'm reverting this line until I can be sure what these do.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 170: x4
"Peg" usually refers to the PCIe lanes attached to the CPU, which do not exist on SKL-U
Hmm. In any case, if dGPUs are only PCIe devices on SKL-U, they wouldn't need any additional configuration/this is handled automatically.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 240: device pci 01.0 on end # Dedicated Graphics Device Yes, but that's not what I meant. While 01:00.0 doesn't appear, coreboot doesn't remove Root Port 1, as it does the NGFF connector.
If the dGPU isn't present with coreboot, it is probably power gated because of Optimus.
I believe that Optimus only provides the OS a way to call BIOS functionality, through ACPI. It's clearly connected, but not the entire issue. However, perhaps if I look at the Optimus table, I'll see what I'm missing.
CB:39002 isn't related, is it? If Optimus on SKL-U doesn't have a PEG port, it wouldn't have a framebuffer, I imagine.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#67).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,916 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/67
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 67:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 240: device pci 01.0 on end # Dedicated Graphics Device
Yes, but that's not what I meant. While 01:00. […]
CB:39002 is about framebuffers that are set up by gfx-init drivers in coreboot. This is completely independent of the way a GPU is connected.
Trying to clear some confusion, I hope I won't make it worse: PEG (PCI Express for Graphics) generally refers to a slot on a mainboard that is dedicated for the gfx card. Sometimes, in the Intel-firmware context it also refers to the PCIe lanes (pins) of the CPU package (what Angel meant). This would show up as `pci 01.0` on bus 0, but SKL-U doesn't have these pins, so there is no `pci 01.0`. Some PCIe lanes of the PCH are used instead, that's all. It makes no difference for Optimus, no difference to gfx drivers, no difference for framebuffers. It's just the way it's physically connected, but that doesn't change anything for the software (beside that coreboot has to enable whatever PCIe port it is connected to).
It's better not to use the term PEG if one doesn't mean a physically present connector (if it's absent how could it be dedicated to gfx?).
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 67:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 240: device pci 01.0 on end # Dedicated Graphics Device
I believe that Optimus only provides the OS a way to call BIOS functionality, through ACPI. It's clearly connected, but not the entire issue. However, perhaps if I look at the Optimus table, I'll see what I'm missing.
This is correct. The ACPI code, however, can call into hidden SMM code which would make analysis much harder.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#68).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,930 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/68
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 68:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 232: [PchSerialIoIndexUart2] = PchSerialIoDisabled,
Done
Must UART pins be programmed in bootblock then?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#69).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Loads TianoCore - Memory - Display (with SkipExtGfxScan disabled and PrimaryDisplay set to iGFX) - with FSP GOP + KBL VBT - Keyboard and touchpad
Requires testing: - Display - with libgfxinit - with FSP GOP + customised KBL VBT, to match vendor's configuration - ACPI - Audio
Does not work: - Booting Fedora 31. Fails with error: "NMI watchdog: detected hard lockup on CPU" or just bootloops - dGPU - Fn keys
Unknown: - EC functioning
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,945 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/69
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#70).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - Internal audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence changed, matches Optimus) - Headphone jack - S3 only works with hotkey
ACPI: - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid not compliant with SW_LID - Brightness "Fn" keys (requires graphics.asl)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - An ata error that I don't remember and wasn't seen again after restart
Unknown: - "ACPI: _SB_.PCI0.LPCB.EC0_: GPE=0x50, IRQ=-1, EC_CMD/EC_SC=0x66, EC_DATA=0x62" - IRQ=-1? - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,945 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/70
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#71).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - Internal audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]
Unknown: - "ACPI: _SB_.PCI0.LPCB.EC0_: GPE=0x50, IRQ=-1, EC_CMD/EC_SC=0x66, EC_DATA=0x62" - IRQ=-1? - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,945 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/71
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#72).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - HDMI port - Internal and HDMI audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]"
Unknown: - "ACPI: _SB_.PCI0.LPCB.EC0_: GPE=0x50, IRQ=-1, EC_CMD/EC_SC=0x66, EC_DATA=0x62" - IRQ=-1? - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,945 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/72
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#73).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - HDMI port - Internal and HDMI audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack and microphone - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]"
Unknown: - "ACPI: _SB_.PCI0.LPCB.EC0_: GPE=0x50, IRQ=-1, EC_CMD/EC_SC=0x66, EC_DATA=0x62" - IRQ=-1? - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,945 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/73
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#74).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - HDMI port - Internal and HDMI audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack and microphone - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]"
Unknown: - "ACPI: _SB_.PCI0.LPCB.EC0_: GPE=0x50, IRQ=-1, EC_CMD/EC_SC=0x66, EC_DATA=0x62" - IRQ=-1? - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 1,945 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/74
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#76).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - HDMI port - Internal and HDMI audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack and microphone - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]"
Unknown: - "ACPI: _SB_.PCI0.LPCB.EC0_: GPE=0x50, IRQ=-1, EC_CMD/EC_SC=0x66, EC_DATA=0x62" - IRQ=-1? - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/76
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 76:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... PS76, Line 34: In that scenario, "Select PCIE card" (which controls the active state of PWR_EN) line over 96 characters
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... PS76, Line 43: gpio_set(DGPU_PWR_EN, 1); // Peg Eval: PWR_EN ActiveHigh; Elk Creek 4: PWR_EN ActiveLow line over 96 characters
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... PS76, Line 45: /* TODO: For the moment, simply notify the user. Otherwise: delay or wait for PWROK? */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... PS76, Line 46: if (!gpio_get(DGPU_PWROK)) { braces {} are not necessary for single statement blocks
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#77).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - HDMI port - Internal and HDMI audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack and microphone - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]"
Unknown: - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/77
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#78).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - HDMI port - Internal and HDMI audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack and microphone - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]"
Unknown: - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,145 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/78
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 78:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... PS76, Line 46: if (!gpio_get(DGPU_PWROK)) {
braces {} are not necessary for single statement blocks
Maybe, but why would it be preferred to avoid using them?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35523
to look at the new patch set (#79).
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
mb/acer: Add Acer Aspire VN7-572G
Add initial support for Acer Aspire VN7-572G.
Works: - Booting Fedora 31 using TianoCore (CorebootPayload) - Display - with FSP GOP + KBL VBT - Keyboard and touchpad - Neither can seem to wake device from S3? - Small touchpad nits - (Perhaps fixed with I2C HID devices declared in devicetree) - USB ports (unable to test type-C) - HDMI port - Internal and HDMI audio
Requires testing: - Display - with libgfxinit - with FSP GOP + a customised KBL VBT, to match vendor's configuration
Does not work: - dGPU (GPIO sequence matches Optimus) - Headphone jack and microphone - S3 only works with hotkey (and cannot be resumed from)
ACPI: - EC is not functioning normally - AC and battery devices appear - Device detected as being perpetually connected to AC - Lid "not compliant to SW_LID" - Brightness "Fn" keys not working (requires graphics.asl, which requires implementation of GMA for Skylake)
Bugs: - "pcieport 0000:00:1d.1: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) AER: device [8086:9d19] error status/mask=00001000/00002000 AER: [12] Timeout" - Fixed by setting ASPM policy in Linux to performance, disabling substates - "[ ..snip ..]ata2.00: failed command: WRITE FPDMA QUEUED[ ..snip ..]"
Unknown: - TPM
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron benjamin.doron00@gmail.com --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/platform.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 19 files changed, 2,145 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/79
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 79:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/ramstage.c:
https://review.coreboot.org/c/coreboot/+/35523/76/src/mainboard/acer/aspire_... PS76, Line 46: if (!gpio_get(DGPU_PWROK)) {
Maybe, but why would it be preferred to avoid using them?
I personally prefer using them. It's just Jenkins being noisy, I guess.