Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61424 )
Change subject: soc/intel/common/gpio: Skip GPIO PAD locking in recovery mode
......................................................................
soc/intel/common/gpio: Skip GPIO PAD locking in recovery mode
The recovery mode is meant to provide fixes for the platform deformity
hence, skip locking the GPIO PAD configuration to provide the same
flexibility to the platform owner while booting in recovery mode.
BUG=b:211950520
TEST=Able to build and boot the brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0f0a3cfb2be7f2a5485679f6a3d8cb4fb407fcf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61424
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
---
M src/soc/intel/common/block/gpio/gpio.c
1 file changed, 3 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
EricR Lai: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index dcec12a..3c5d3f3 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -13,6 +13,7 @@
#include <intelblocks/itss.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
+#include <security/vboot/vboot_common.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <stdlib.h>
@@ -616,8 +617,8 @@
int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action lock_action)
{
- /* Skip locking GPIO PAD in early stages */
- if (ENV_ROMSTAGE_OR_BEFORE)
+ /* Skip locking GPIO PAD in early stages or in recovery mode */
+ if (ENV_ROMSTAGE_OR_BEFORE || vboot_recovery_mode_enabled())
return -1;
const struct gpio_lock_config pads = {
--
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Gerrit-Change-Number: 61424
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Attention is currently required from: Patrick Rudolph.
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61433
to look at the new patch set (#3).
Change subject: soc/intel/skylake: Choose pcr write to disable HECI1
......................................................................
soc/intel/skylake: Choose pcr write to disable HECI1
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config on
Skylake to perform heci1 disabling using pcr writes.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/finalize.c
2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61433/3
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61373 )
Change subject: mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
......................................................................
mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:R
Add supported memory parts in "mem_parts_used.txt" and generate
the SPD ID 0x04 for the parts.
Shuboz memory table as follow:
value Vendor Part number
0000 MICRON MT40A512M16TB-062E:J
0001 HYNIX H5AN8G6NCJR-XNC
0010 MICRON MT40A1G16KD-062E:E
0011 SAMSUNG K4AAG165WA-BCWE
0100 MICRON MT40A512M16TB-062E:R
BUG=b:216571906
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com>
Change-Id: Ib0100456457adabed6fd6615e0873de2cf9acb98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61373
Reviewed-by: Kangheui Won <khwon(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
M src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
M src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
3 files changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kane Chen: Looks good to me, but someone else must approve
Kangheui Won: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
index 3168806..3875882 100644
--- a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
+++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc
@@ -8,3 +8,4 @@
SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC
SPD_SOURCES += spd/ddr4/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT40A1G16KD-062E:E
SPD_SOURCES += spd/ddr4/set-0/spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE
+SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 4(0b0100) Parts = MT40A512M16TB-062E:R
diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
index a38e73f..a1893db 100644
--- a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
+++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt
@@ -8,3 +8,4 @@
H5AN8G6NCJR-XNC 1 (0001)
MT40A1G16KD-062E:E 2 (0010)
K4AAG165WA-BCWE 3 (0011)
+MT40A512M16TB-062E:R 4 (0100)
diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
index e547919..b4caa40 100644
--- a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
+++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt
@@ -11,3 +11,4 @@
H5AN8G6NCJR-XNC, 1
MT40A1G16KD-062E:E, 2
K4AAG165WA-BCWE, 3
+MT40A512M16TB-062E:R, 4
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61407 )
Change subject: soc/intel/common/cse: skip heci_init() if HECI1 is disabled
......................................................................
soc/intel/common/cse: skip heci_init() if HECI1 is disabled
If the HECI1 PCI device is disabled, either via devicetree or other
method (HAP, me_cleaner), then we don't want/need to program a BAR,
set the PCI config, or call heci_reset(), as the latter will result
in a 15s timeout delay when booting.
Test: build/boot Purism Librem 13v2, verify heci_reset()
timeout delay is no longer present.
Change-Id: I0babe417173d10e37327538dc9e7aae980225367
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61407
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 7d6faba..32f6d4f 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -94,6 +94,10 @@
u16 pcireg;
+ /* Check if device enabled */
+ if (!is_cse_enabled())
+ return;
+
/* Assume it is already initialized, nothing else to do */
if (get_cse_bar(dev))
return;
--
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Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Tim Chu.
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61431
to look at the new patch set (#4).
Change subject: soc/intel/common/cse: Rework heci_disable function
......................................................................
soc/intel/common/cse: Rework heci_disable function
This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the
compilation failure.
Finally, rename heci_disable() function to heci1_disable() to make it
more meaningful.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
---
M src/soc/intel/alderlake/smihandler.c
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/disable_heci.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/elkhartlake/smihandler.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/jasperlake/smihandler.c
M src/soc/intel/skylake/include/soc/pcr_ids.h
M src/soc/intel/tigerlake/smihandler.c
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
13 files changed, 79 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/4
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61409 )
Change subject: mb/google/brya: Remove EC_GOOGLE_CHROMEEC_ACPI_MEMMAP Kconfig
......................................................................
mb/google/brya: Remove EC_GOOGLE_CHROMEEC_ACPI_MEMMAP Kconfig
The EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is intended for Chrome microchip ECs
only, which have different requirements as to the amount of memory
mapped space they can claim. The brya family of boards does not use
any microchip ECs, therefore remove this Kconfig.
BUG=b:214460174
TEST=boot brya4es to kernel, no EC errors seen in cbmem log, EC software
sync still works.
Change-Id: I6e9858f29d079140ec43341de90f222b03986edb
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61409
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
EricR Lai: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 7de078a..1a9f5cc 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -19,7 +19,6 @@
select DRIVERS_SPI_ACPI
select DRIVERS_WIFI_GENERIC
select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_SKUID
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61147 )
Change subject: mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCM
......................................................................
mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCM
Drawcia's MIPI camera sensor and VCM both share the same reset GPIO
from the PCH. The current power sequence does not take this into
account, and this leads to an unbalanced ref count of the reset GPIO,
which can cause one or the other of the devices to reset unexpectedly.
This patch corrects that by explicitly sequencing the reset GPIO for
both devices, which the builtin refcounting of this driver will
automatically handle.
BUG=b:214665783
TEST=Build, boot to OS and check VCM once camera stream off
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61147
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/dedede/variants/drawcia/overridetree.cb
1 file changed, 10 insertions(+), 5 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index cb3ff48..2b32e9b 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -314,12 +314,13 @@
register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset
#_ON
- register "on_seq.ops_cnt" = "5"
+ register "on_seq.ops_cnt" = "6"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
- register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
- register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+ register "on_seq.ops[4]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+ register "on_seq.ops[5]" = "SEQ_OPS_GPIO_ENABLE(2, 0)"
#_OFF
register "off_seq.ops_cnt" = "4"
@@ -342,12 +343,16 @@
register "low_power_probe" = "1"
register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_D12" #reset
#_ON
- register "on_seq.ops_cnt" = "1"
+ register "on_seq.ops_cnt" = "2"
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
#_OFF
- register "off_seq.ops_cnt" = "1"
+ register "off_seq.ops_cnt" = "2"
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
+
device i2c 0C on end
end
chip drivers/intel/mipi_camera
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: ShawnX Tu <shawnx.tu(a)intel.com>
Gerrit-CC: Tian Shu Qiu <tian.shu.qiu(a)intel.com>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61146 )
Change subject: driver/intel/mipi_camera: Increase max power ops count to 6
......................................................................
driver/intel/mipi_camera: Increase max power ops count to 6
Current max count for camera power ops is 5 which is not sufficient.
If we increase the ops by 1 in current variants the compiler
will not throw error for intel mipi camera driver.
Hence increase current max count for camera power ops to 6 from 5.
BUG=b:214665783
TEST=Build and boot to OS
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61146
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/drivers/intel/mipi_camera/chip.h
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 55e9f33f..9d8291e 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -12,7 +12,7 @@
#define MAX_LINK_FREQ_ENTRIES 4
#define MAX_CLK_CONFIGS 2
#define MAX_GPIO_CONFIGS 4
-#define MAX_PWR_OPS 5
+#define MAX_PWR_OPS 6
#define MAX_GUARDED_RESOURCES 10
#define IMGCLKOUT_0 0
#define IMGCLKOUT_1 1
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80
Gerrit-Change-Number: 61146
Gerrit-PatchSet: 7
Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged