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Change subject: util/lint: Remove SuperIO from checkpatch spellcheck
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61434/comment/c4e13d9e_872008a8
PS1, Line 7: Remove
> You replace it by the lowercase spelling?
Thanks Paul, I ran a bunch of experiments on this - I definitely meant to just remove it.
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Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61431
to look at the new patch set (#5).
Change subject: soc/intel/common/cse: Rework heci_disable function
......................................................................
soc/intel/common/cse: Rework heci_disable function
This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the
compilation failure.
Finally, rename heci_disable() function to heci1_disable() to make it
more meaningful.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
---
M src/soc/intel/alderlake/smihandler.c
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/disable_heci.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/elkhartlake/smihandler.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/jasperlake/smihandler.c
M src/soc/intel/skylake/include/soc/pcr_ids.h
M src/soc/intel/tigerlake/smihandler.c
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
13 files changed, 78 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/5
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61431 )
Change subject: soc/intel/common/cse: Rework heci_disable function
......................................................................
Patch Set 4:
(6 comments)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/61431/comment/870fabac_46e5921a
PS3, Line 22: only done
> nit: only be done
Ack
https://review.coreboot.org/c/coreboot/+/61431/comment/ca35c12a_1e58d30e
PS3, Line 22: From CNL PCH onwards,`HECI1` disabling can only done using
: non-posted sideband write after FSP-S sets the postboot_sai
: attribute.
: Use this config to include common CSE block to make
: HECI function disable in SMM mod
> Reordering of statements may require, something like below.. […]
Ack
https://review.coreboot.org/c/coreboot/+/61431/comment/cad78f5b_2526f2fa
PS3, Line 25: make
: HECI
> nit: make the HECI function in the SMM mode
You mean HECI function *disable* in the SMM mode.
https://review.coreboot.org/c/coreboot/+/61431/comment/c1150470_b294c16b
PS3, Line 43: Prior to postboot_sai enforcement since CNL PCH, `HECI1` device were
: disable using private configuration register (PCR) write.
> > This mechanism is available starting from CNL PCH. […]
Ack
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/61431/comment/55063aca_9e30389c
PS3, Line 493: PCR
> PCR.
Ack
https://review.coreboot.org/c/coreboot/+/61431/comment/adf103f3_74f31a70
PS3, Line 494: PSF port id for disabling cse is expected to be different between
: * SoC generation hence, allow SoC to implement the override.
> It may need rephrasing...
Ack
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Change subject: crossgcc: Update acpica from 20210331 to 20211217
......................................................................
Patch Set 11: Code-Review+2
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Change subject: IASL: Ignore IASL's "Missing dependency" warning
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
Patchset:
PS8:
Martin is setting a reminder for us to take a look at cleaning this up in 3 months
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Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS5:
> A bit update by exposing the generic p2sb_dev_sbi_read and p2sb_dev_sbi_write into p2sblib.
If no further comment, can we consider to move forward as baseline?
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