coreboot-gerrit January 2022

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Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3
by Felix Held (Code Review) 29 Jan '22

29 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59362 ) Change subject: soc/intel/alderlake: Enable CPPCv3 ...................................................................... soc/intel/alderlake: Enable CPPCv3 The patch defines the following helper functions: get_cpu_scaling_factor(): Returns scaling factors of big and small core. cpu_is_nominal_freq_supported(): Returns true if CPU supports Nominal Frequency, otherwise false. cpu_is_nominal_freq_supported(): Check CPU supports nominal frequency or not. The patch also enables CPPCv3 support for Intel Alder Lake which is based on hybrid core architecture. TEST=Verified Nominal Frequency and Nominal Performance are getting updated for ADL-P small and big cores correctly. Signed-off-by: Sridahr Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59362 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/cpu.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 04e113a..ac8c2e3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -63,6 +63,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index b6dc898..3b3a7a2 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -90,6 +90,17 @@ return CPUID_CORE_TYPE_INTEL_CORE; } +void soc_get_scaling_factor(u16 *big_core_scal_factor, u16 *small_core_scal_factor) +{ + *big_core_scal_factor = 127; + *small_core_scal_factor = 100; +} + +bool soc_is_nominal_freq_supported(void) +{ + return true; +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Gerrit-Change-Number: 59362 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Felix Held (Code Review) 29 Jan '22

29 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core The patch implements ACPI CPPCv3 package. It implements and updates the following methods: generate_cppc_entries(): Updates method to support CPPCv3 package acpi_get_cpu_nominal_freq(): Calculates CPU's nominal frequency acpi_get_cpu_nomi_perf(): Calculates nominal performance for big and small cores. acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement _CPC method. acpigen_cppc_update_nominal_freq_perf(): It updates CPPC3 package if cpu supports Nominal Frequency. It generates ACPI code which sets Nominal Frequency and updates Nominal Performance. It uses below calculation to update the Nominal Frequency and Nominal Performance: Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency Nominal Performance = Max non-turn ratio * cpu scaling factor CPU scaling factor varies in the hybrid core environment. So, the generated ACPI code updates Nominal Performance based on the CPU's scaling factor. TEST=Verified CPPCv3 package is getting created in the SSDT table. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Signed-off-by: ravindr1 <ravindra(a)intel.com> Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59359 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 3 files changed, 78 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index b827c58..53fa907 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -372,6 +372,11 @@ static void generate_cppc_entries(int core_id) { + u32 version = CPPC_VERSION_2; + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + version = CPPC_VERSION_3; + if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && cpuid_eax(6) & CPUID_6_EAX_ISST)) return; @@ -379,12 +384,15 @@ /* Generate GCPC package in first logical core */ if (core_id == 0) { struct cppc_config cppc_config; - cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + cpu_init_cppc_config(&cppc_config, version); acpigen_write_CPPC_package(&cppc_config); } /* Write _CPC entry for each logical core */ - acpigen_write_CPPC_method(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + acpigen_write_CPPC_hybrid_method(core_id); + else + acpigen_write_CPPC_method(); } __weak void soc_power_states_generation(int core_id, diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index cbfaed8..70e6329 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -8,6 +8,9 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> +#define CPPC_NOM_FREQ_IDX 22 +#define CPPC_NOM_PERF_IDX 3 + DECLARE_SPIN_LOCK(cpu_lock); static u8 global_cpu_type[CONFIG_MAX_CPUS]; @@ -56,4 +59,61 @@ } } +static void acpi_get_cpu_nomi_perf(u16 *small_core_nom_perf, u16 *big_core_nom_perf) +{ + u16 big_core_scal_factor, small_core_scal_factor; + u8 max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); + + soc_get_scaling_factor(&big_core_scal_factor, &small_core_scal_factor); + + *big_core_nom_perf = (u16)((max_non_turbo_ratio * big_core_scal_factor) / 100); + + *small_core_nom_perf = (u16)((max_non_turbo_ratio * small_core_scal_factor) / 100); +} + +static u16 acpi_get_cpu_nominal_freq(void) +{ + return cpu_get_max_non_turbo_ratio() * cpu_get_bus_frequency(); +} + +/* Updates Nominal Frequency and Nominal Performance */ +static void acpigen_cppc_update_nominal_freq_perf(const char *pkg_path, s32 core_id) +{ + u16 small_core_nom_perf, big_core_nom_perf; + + if (!soc_is_nominal_freq_supported()) + return; + + acpi_get_cpu_nomi_perf(&small_core_nom_perf, &big_core_nom_perf); + + if (global_cpu_type[core_id]) + acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, big_core_nom_perf); + else + acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, + small_core_nom_perf); + + /* Update CPU's nominal frequency */ + acpigen_set_package_element_int(pkg_path, CPPC_NOM_FREQ_IDX, + acpi_get_cpu_nominal_freq()); +} + +void acpigen_write_CPPC_hybrid_method(s32 core_id) +{ + char pkg_path[16]; + + if (core_id == 0) + snprintf(pkg_path, sizeof(pkg_path), CPPC_PACKAGE_NAME, 0); + else + snprintf(pkg_path, sizeof(pkg_path), + CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0); + + acpigen_write_method("_CPC", 0); + + /* Update nominal performance and nominal frequency */ + acpigen_cppc_update_nominal_freq_perf(pkg_path, core_id); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(pkg_path); + acpigen_pop_len(); +} + BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, run_set_cpu_type, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 2634145..d05ddf3 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -18,6 +18,12 @@ CPUID_UNKNOWN = 0xff, }; +/* Gets the scaling factor for small and big core */ +void soc_get_scaling_factor(u16 *big_core_scal_factor, u16 *small_core_scal_factor); + +/* Generates ACPI code to define _CPC control method */ +void acpigen_write_CPPC_hybrid_method(int core_id); + /* Forward declare the power state struct here */ struct chipset_power_state; @@ -125,4 +131,6 @@ */ enum core_type get_soc_cpu_type(void); +/* Check if CPU supports Nominal frequency or not */ +bool soc_is_nominal_freq_supported(void); #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ravindr1 <ravindra(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot.
by Sudheer Amrabadi (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Ravi kumar, Sudheer Amrabadi. Sudheer Amrabadi has uploaded a new patch set (#21) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot. ...................................................................... sc7280: Add Modem region to avoid modem cleanup in Secboot reboot. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: T Michael Turney <quic_mturney(a)quicinc.com> Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/carve_out.c M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 5 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58545/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/guybrush: Add variant to disable HDMI
by Bao Zheng (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Paul Menzel, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61314 ) Change subject: mb/google/guybrush/guybrush: Add variant to disable HDMI ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61314/comment/db3ca8bd_52f40aa2 PS4, Line 9: For one specific type of APU > make sense. […] Done. Change the way to detect, more specifically. -- To view, visit https://review.coreboot.org/c/coreboot/+/61314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93fca8cf9870533da1bcca5fa28ff22085e65beb Gerrit-Change-Number: 61314 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 28 Jan 2022 14:50:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Add variant to disable HDMI
by Bao Zheng (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61361 ) Change subject: mb/amd/majolica: Add variant to disable HDMI ...................................................................... Patch Set 4: (1 comment) File src/mainboard/amd/majolica/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/61361/comment/0ee767aa_094eb50b PS3, Line 127: *dxio_descs = majolica_czn_dxio_descriptors; > this line is missing Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Gerrit-Change-Number: 61361 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Jan 2022 14:48:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Refer to vboot source consistently
by Patrick Georgi (Code Review) 29 Jan '22

29 Jan '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61427 ) Change subject: libpayload: Refer to vboot source consistently ...................................................................... libpayload: Refer to vboot source consistently Don't assume that libpayload is built from a fully checked out coreboot tree. There's already an override when building vboot, so reuse that override when referring to its header files. Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Change-Id: I503c69a593dd68b3a974fbdbb64d7bb25d6c7f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61427 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M payloads/libpayload/Makefile.inc M payloads/libpayload/tests/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 01c3ede..430994b 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -62,7 +62,7 @@ INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) INCLUDES += -include include/kconfig.h -include include/compiler.h INCLUDES += -I$(coreboottop)/src/commonlib/bsd/include -INCLUDES += -I$(coreboottop)/3rdparty/vboot/firmware/include +INCLUDES += -I$(VBOOT_SOURCE)/firmware/include CFLAGS += $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer diff --git a/payloads/libpayload/tests/Makefile.inc b/payloads/libpayload/tests/Makefile.inc index e1c2a23..529524c 100644 --- a/payloads/libpayload/tests/Makefile.inc +++ b/payloads/libpayload/tests/Makefile.inc @@ -34,7 +34,7 @@ TEST_CFLAGS += -Iinclude -Iinclude/mock TEST_CFLAGS += -I$(coreboottop)/src/commonlib/bsd/include TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) -TEST_CFLAGS += -I$(coreboottop)/3rdparty/vboot/firmware/include +TEST_CFLAGS += -I$(VBOOT_SOURCE)/firmware/include # Test specific includes TEST_CFLAGS += -I$(testsrc)/include -- To view, visit https://review.coreboot.org/c/coreboot/+/61427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503c69a593dd68b3a974fbdbb64d7bb25d6c7f63 Gerrit-Change-Number: 61427 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: temp
by Bao Zheng (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/61450 to review the following change. Change subject: temp ...................................................................... temp Change-Id: Ifd5dbd1ca061fcc20e45dbc8fb1211a5a8144bbc Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- D util/coreboot-configurator/images/coreboot-configurator.gif 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61450/1 diff --git a/util/coreboot-configurator/images/coreboot-configurator.gif b/util/coreboot-configurator/images/coreboot-configurator.gif deleted file mode 100644 index 64e0a2f..0000000 --- a/util/coreboot-configurator/images/coreboot-configurator.gif +++ /dev/null Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/61450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5dbd1ca061fcc20e45dbc8fb1211a5a8144bbc Gerrit-Change-Number: 61450 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/majolica: Add variant to disable HDMI
by Bao Zheng (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Zheng Bao. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61361 to look at the new patch set (#4). Change subject: mb/amd/majolica: Add variant to disable HDMI ...................................................................... mb/amd/majolica: Add variant to disable HDMI For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/majolica/port_descriptors.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/61361/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Gerrit-Change-Number: 61361 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/guybrush: Add variant to disable HDMI
by Bao Zheng (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Bao Zheng, Paul Menzel, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61314 to look at the new patch set (#8). Change subject: mb/google/guybrush/guybrush: Add variant to disable HDMI ...................................................................... mb/google/guybrush/guybrush: Add variant to disable HDMI For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c BUG=b:215432928 Change-Id: I93fca8cf9870533da1bcca5fa28ff22085e65beb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/guybrush/variants/guybrush/variant.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/61314/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93fca8cf9870533da1bcca5fa28ff22085e65beb Gerrit-Change-Number: 61314 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add the fw SPL to amdfw.cfg
by Rob Barnes (Code Review) 29 Jan '22

29 Jan '22

Attention is currently required from: Bao Zheng, Zheng Bao. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61445 ) Change subject: mb/google/guybrush: Add the fw SPL to amdfw.cfg ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Was this tested on guybrush? I don't know what an SPL table is, so I'm not sure what exactly needs to be tested to ensure this doesn't cause any regressions. -- To view, visit https://review.coreboot.org/c/coreboot/+/61445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268a92c9916b261fbc899ebb72f75f7a3f12c441 Gerrit-Change-Number: 61445 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 28 Jan 2022 14:26:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2022