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Change in coreboot[master]: drivers/i2c/cs35l53: Add driver for generating device in SSDT
by Vitaly Rodionov (Code Review) 28 Jan '22

28 Jan '22

Vitaly Rodionov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61448 ) Change subject: drivers/i2c/cs35l53: Add driver for generating device in SSDT ...................................................................... drivers/i2c/cs35l53: Add driver for generating device in SSDT This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606 Signed-off-by: Stefan Binding <sbinding(a)opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> --- A src/drivers/i2c/cs35l53/Kconfig A src/drivers/i2c/cs35l53/Makefile.inc A src/drivers/i2c/cs35l53/chip.h A src/drivers/i2c/cs35l53/cs35l53.c 4 files changed, 263 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/61448/1 diff --git a/src/drivers/i2c/cs35l53/Kconfig b/src/drivers/i2c/cs35l53/Kconfig new file mode 100644 index 0000000..38d6617 --- /dev/null +++ b/src/drivers/i2c/cs35l53/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_I2C_CS35L53 + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/i2c/cs35l53/Makefile.inc b/src/drivers/i2c/cs35l53/Makefile.inc new file mode 100644 index 0000000..21a749f --- /dev/null +++ b/src/drivers/i2c/cs35l53/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_CS35L53) += cs35l53.c diff --git a/src/drivers/i2c/cs35l53/chip.h b/src/drivers/i2c/cs35l53/chip.h new file mode 100644 index 0000000..e477355 --- /dev/null +++ b/src/drivers/i2c/cs35l53/chip.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> + +enum cs35l53_boost_ind_nanohenrys { + BOOST_IND_1000_NH = 1000, + BOOST_IND_1200_NH = 1200, + BOOST_IND_1500_NH = 1500, + BOOST_IND_2200_NH = 2200, +}; + +enum cs35l53_asp_sdout_hiz { + ASP_SDOUT_LOGIC0_UNUSED_LOGIC0_DISABLED = 0, + ASP_SDOUT_HIZ_UNUSED_LOGIC0_DISABLED = 1, + ASP_SDOUT_LOGIC0_UNUSED_HIZ_DISABLED = 2, + ASP_SDOUT_HIZ_UNUSED_HIZ_DISABLED = 3, +}; + +enum cs35L53_gpio1_src { + GPIO1_SRC_HIGH_IMPEDANCE = 0, + GPIO1_SRC_GPIO = 1, + GPIO1_SRC_SYNC = 2, + GPIO1_SRC_MCLK_INPUT = 3, +}; + +enum cs35L53_gpio2_src { + GPIO2_SRC_HIGH_IMPEDANCE = 0, + GPIO2_SRC_GPIO = 1, + GPIO2_SRC_OPEN_DRAIN = 2, + GPIO2_SRC_MCLK_INPUT = 3, + GPIO2_SRC_PUSH_PULL_INTB = 4, + GPIO2_SRC_PUSH_PULL_INT = 5, +}; + +/* + * Cirrus Logic CS35L53 Audio Codec devicetree bindings + * linux/Documentation/devicetree/bindings/sound/cirrus,cs35l53.yaml + */ +struct drivers_i2c_cs35l53_config { + const char *name; /* ACPI Device Name */ + + /* Interrupt configuration */ + struct acpi_irq irq; + + /* Use GPIO based interrupt instead of PIRQ */ + struct acpi_gpio irq_gpio; + + /* Use GPIO based reset gpio */ + struct acpi_gpio reset_gpio; + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned int bus_speed; + + /* Define cs35l53 parameters */ + /* + * cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. + * Configures the peak current by monitoring the current through the boost FET. + * Range starts at 1600 mA and goes to a maximum of 4500 mA with increments + * of 50 mA. See section 4.3.6 of the datasheet for details. + */ + unsigned int boost_peak_milliamp; + + /* + * cirrus,boost-ind-nanohenry : Boost inductor value, expressed in nH. Valid + * values include 1000, 1200, 1500 and 2200. + */ + enum cs35l53_boost_ind_nanohenrys boost_ind_nanohenry; + + /* + * cirrus,boost-cap-microfarad : Total equivalent boost capacitance on the VBST + * and VAMP pins, derated at 11 volts DC. The value must be rounded to the + * nearest integer and expressed in uF. + */ + unsigned int boost_cap_microfarad; + + /* + * cirrus,asp-sdout-hiz : Audio serial port SDOUT Hi-Z control. Sets the Hi-Z + * configuration for SDOUT pin of amplifier. + * 0 = Logic 0 during unused slots, and while all transmit channels disabled + * 1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled + * 2 = Logic 0 during unused slots, but Hi-Z while all transmit channels disabled + * 3 = Hi-Z during unused slots and while all transmit channels disabled + */ + enum cs35l53_asp_sdout_hiz asp_sdout_hiz; + + /* + * cirrus,gpio1-polarity-invert : Boolean which specifies whether the GPIO1 + * level is inverted. + */ + bool gpio1_polarity_invert; + + /* + * cirrus,gpio1-output-enable : Boolean which specifies whether the GPIO1 pin + * is configured as an output. + */ + bool gpio1_output_enable; + + /* + * cirrus,gpio1-src-select : Configures the function of the GPIO1 pin. + * Note that the options are different from the GPIO2 pin + * 0 = High Impedance (Default) + * 1 = GPIO + * 2 = Sync + * 3 = MCLK input + */ + enum cs35L53_gpio1_src gpio1_src_select; + + /* + * cirrus,gpio2-polarity-invert : Boolean which specifies whether the GPIO2 + * level is inverted. + */ + bool gpio2_polarity_invert; + + /* + * cirrus,gpio2-output-enable : Boolean which specifies whether the GPIO2 pin + * is configured as an output. + */ + bool gpio2_output_enable; + + /* + * cirrus,gpio2-src-select : Configures the function of the GPIO2 pin. + * Note that the options are different from the GPIO2 pin + * 0 = High Impedance (Default) + * 1 = GPIO + * 2 = Open Drain INTB + * 3 = MCLK input + * 4 = Push-pull INTB (active low) + * 5 = Push-pull INT (active high) + */ + enum cs35L53_gpio2_src gpio2_src_select; + +}; diff --git a/src/drivers/i2c/cs35l53/cs35l53.c b/src/drivers/i2c/cs35l53/cs35l53.c new file mode 100644 index 0000000..83dde36 --- /dev/null +++ b/src/drivers/i2c/cs35l53/cs35l53.c @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <device/device.h> +#include <device/path.h> + +#include "chip.h" + +#define CS35L53_ACPI_HID "CSC3541" + +static void cs35l53_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_cs35l53_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd; + int gpio_index = 0; + + if (!scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", CS35L53_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + /* Use either Interrupt() or GpioInt() */ + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + + /* for cs35l53 reset gpio */ + if (config->reset_gpio.pin_count) + acpi_device_write_gpio(&config->reset_gpio); + + acpigen_write_resourcetemplate_footer(); + + /* AAD Child Device Properties */ + dsd = acpi_dp_new_table("_DSD"); + if (config->irq_gpio.pin_count) + acpi_dp_add_gpio(dsd, "irq-gpios", path, + gpio_index++, /* Index = 0 */ + 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ + config->irq_gpio.active_low); + if (config->reset_gpio.pin_count) + acpi_dp_add_gpio(dsd, "reset-gpios", path, + gpio_index++, /* Index = 0 or 1 (if irq gpio is written). */ + 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ + config->reset_gpio.active_low); + + if ((config->boost_peak_milliamp > 4500) || + (config->boost_peak_milliamp < 1600) || + (config->boost_peak_milliamp % 50)) + { + printk(BIOS_ERR, "%s: Incorrect boost_peak_milliamp(%d). Using default of 4500 mA\n", + __func__, config->boost_peak_milliamp); + config->boost_peak_milliamp = 4500; + } + acpi_dp_add_integer(dsd, "cirrus,boost-peak-milliamp", config->boost_peak_milliamp); + + acpi_dp_add_integer(dsd, "cirrus,boost-ind-nanohenry", config->boost_ind_nanohenry); + acpi_dp_add_integer(dsd, "cirrus,boost-cap-microfarad", config->boost_cap_microfarad); + acpi_dp_add_integer(dsd, "cirrus,asp-sdout-hiz", config->asp_sdout_hiz); + acpi_dp_add_integer(dsd, "cirrus,gpio1-polarity-invert", config->gpio1_polarity_invert ? 1 : 0); + acpi_dp_add_integer(dsd, "cirrus,gpio1-output-enable", config->gpio1_output_enable ? 1 : 0); + acpi_dp_add_integer(dsd, "cirrus,gpio1-src-select", config->gpio1_src_select); + acpi_dp_add_integer(dsd, "cirrus,gpio2-polarity-invert", config->gpio2_polarity_invert ? 1 : 0); + acpi_dp_add_integer(dsd, "cirrus,gpio2-output-enable", config->gpio2_output_enable ? 1 : 0); + acpi_dp_add_integer(dsd, "cirrus,gpio2-src-select", config->gpio2_src_select); + + /* Write Device Property Hierarchy */ + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device, config->irq.pin); +} + +static const char *cs35l53_acpi_name(const struct device *dev) +{ + struct drivers_i2c_cs35l53_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + + snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); + return name; +} + +static struct device_operations cs35l53_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = cs35l53_acpi_name, + .acpi_fill_ssdt = cs35l53_fill_ssdt, +}; + +static void cs35l53_enable(struct device *dev) +{ + dev->ops = &cs35l53_ops; +} + +struct chip_operations drivers_i2c_cs35l53_ops = { + CHIP_NAME("Cirrus Logic CS35L53 Audio Codec") + .enable_dev = cs35l53_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/61448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606 Gerrit-Change-Number: 61448 Gerrit-PatchSet: 1 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/nissa: Add devicetree
by Krishna P Bhat D (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 ) Change subject: mb/google/nissa: Add devicetree ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb: https://review.coreboot.org/c/coreboot/+/61141/comment/68fa6ee7_bdd835f7 PS4, Line 112: device ref tcss_dma0 on end Not applicable for ADL-N. https://review.coreboot.org/c/coreboot/+/61141/comment/591f1725_d3e6d722 PS4, Line 113: device ref tcss_dma1 on end Not applicable for ADL-N. -- To view, visit https://review.coreboot.org/c/coreboot/+/61141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Gerrit-Change-Number: 61141 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 10:21:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree
by Maulik V Vaghela (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61331 ) Change subject: intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61331/comment/4a411947_0a69f786 PS6, Line 7: intel/common/blk/pcie: Add Null and 0 count check in pcie_rp_update_devtree > try to reflow this within 72 char in a line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Gerrit-Change-Number: 61331 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 10:13:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree
by Maulik V Vaghela (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61331 to look at the new patch set (#7). Change subject: intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree ...................................................................... intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtree pcie_rp_update_devicetree function takes pcie_rp_group strcuture as an argument and SoC code passes the parameter in this structure. This pointer can be NULL and common code may try to dereference this NULL pointer. Also, group might have no data and SoC may pass this by indicating group count as zero (For example, for CPU or TBT root ports). These checks will prevent function from executing redundant code and returning early from the call as it's not required. BUG=b:210933428 BRANCH=None TEST=check if function returns early for group count 0 and there is no issue while booting board in case group count = 0. Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/block/pcie/pcie_rp.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61331/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Gerrit-Change-Number: 61331 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "soc/intel/adl: Skip sending MBP HOB to save boot time"
by Maulik V Vaghela (Code Review) 28 Jan '22

28 Jan '22

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61447 ) Change subject: Revert "soc/intel/adl: Skip sending MBP HOB to save boot time" ...................................................................... Revert "soc/intel/adl: Skip sending MBP HOB to save boot time" This reverts commit 9a7fbbc98e8610a0a5314470edd8d5dafe676a06. Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/61447/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 790aa99..32bf63f 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -207,9 +207,6 @@ /* Skip GPIO configuration from FSP */ m_cfg->GpioOverride = 0x1; - /* Skip generation of MBP HOB from FSP. coreboot doesn't consume it */ - m_cfg->SkipMbpHob = 1; - /* CNVi DDR RFI Mitigation */ m_cfg->CnviDdrRfim = config->CnviDdrRfim; } -- To view, visit https://review.coreboot.org/c/coreboot/+/61447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff Gerrit-Change-Number: 61447 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Fix issue of clearing watchdog status
by Rex-BC Chen (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61446 ) Change subject: soc/mediatek/mt8186: Fix issue of clearing watchdog status ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f Gerrit-Change-Number: 61446 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 09:58:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Fix issue of clearing watchdog status
by Rex-BC Chen (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61446 ) Change subject: soc/mediatek/mt8186: Fix issue of clearing watchdog status ...................................................................... soc/mediatek/mt8186: Fix issue of clearing watchdog status Wrong implementation for clearing watchdog status. The setting value should be: value of wdt mode | 0x22000000. BUG=b:204229208 TEST=check watchdog status is cleared. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f --- M src/soc/mediatek/common/include/soc/wdt.h M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8186/wdt.c M src/soc/mediatek/mt8195/wdt.c 4 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/61446/1 diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index 6b27bef..cd43134 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -39,6 +39,6 @@ static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; int mtk_wdt_init(void); -void mtk_wdt_clr_status(uint32_t wdt_sta); +void mtk_wdt_clr_status(void); #endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 6e1b761..587e50f 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -6,7 +6,7 @@ #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> -__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ } +__weak void mtk_wdt_clr_status(void) { /* do nothing */ } int mtk_wdt_init(void) { @@ -15,7 +15,7 @@ /* Writing mode register will clear status register */ wdt_sta = read32(&mtk_wdt->wdt_status); - mtk_wdt_clr_status(wdt_sta); + mtk_wdt_clr_status(); printk(BIOS_INFO, "WDT: Status = %#x\n", wdt_sta); diff --git a/src/soc/mediatek/mt8186/wdt.c b/src/soc/mediatek/mt8186/wdt.c index d0e13d9..fbc9bb9 100644 --- a/src/soc/mediatek/mt8186/wdt.c +++ b/src/soc/mediatek/mt8186/wdt.c @@ -9,9 +9,12 @@ #include <soc/addressmap.h> #include <soc/wdt.h> -#define MTK_WDT_CLR_STATUS 0x22000000 +#define MTK_WDT_CLR_STATUS_VAL 0x22 -void mtk_wdt_clr_status(uint32_t wdt_sta) +DEFINE_BITFIELD(MTK_WDT_CLR_STATUS, 31, 24) + +void mtk_wdt_clr_status(void) { - write32(&mtk_wdt->wdt_mode, wdt_sta | MTK_WDT_CLR_STATUS); + SET32_BITFIELDS(&mtk_wdt->wdt_mode, + MTK_WDT_CLR_STATUS, MTK_WDT_CLR_STATUS_VAL); } diff --git a/src/soc/mediatek/mt8195/wdt.c b/src/soc/mediatek/mt8195/wdt.c index c000bf7..fcee3db 100644 --- a/src/soc/mediatek/mt8195/wdt.c +++ b/src/soc/mediatek/mt8195/wdt.c @@ -6,7 +6,7 @@ #define MTK_WDT_CLR_STATUS 0x230001FF -void mtk_wdt_clr_status(uint32_t wdt_sta) +void mtk_wdt_clr_status(void) { write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f Gerrit-Change-Number: 61446 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Support DRAM fast calibration using blob
by Rex-BC Chen (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61133 ) Change subject: soc/mediatek/mt8186: Support DRAM fast calibration using blob ...................................................................... Patch Set 25: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc Gerrit-Change-Number: 61133 Gerrit-PatchSet: 25 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 09:55:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add register protect control for MT6366
by Rex-BC Chen (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61390 ) Change subject: soc/mediatek/mt8186: Add register protect control for MT6366 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94d73d9c8a137444988e65c3709d29a3a4c03c5b Gerrit-Change-Number: 61390 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 09:55:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add GPIO table for nissa
by Reka Norman (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Tim Wawrzynczak. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60995 ) Change subject: mb/google/brya: Add GPIO table for nissa ...................................................................... Patch Set 8: (4 comments) Patchset: PS8: > There are few open comments but I don't think these are related to the code directly, hence +2. Yeah, I think the only unresolved issues are checking the WWAN and SSD power sequencing requirements. But I don't think those need to block this going in. I'll file bugs for checking the requirements on Monday. File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/60995/comment/bf6657c3_9381977a PS1, Line 374: NF1 > EC pinmap has been updated : https://chromium-review.googlesource. […] Done File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/60995/comment/52f669f7_528b7156 PS3, Line 409: }; > I'll check if we have datasheets yet. Marking resolved. I'll file a bug to check the requirements on Monday. File src/mainboard/google/brya/variants/baseboard/nissa/gpio.c: https://review.coreboot.org/c/coreboot/+/60995/comment/52d8a96e_af0933e7 PS6, Line 109: EN_PP3300_UCAM_X > If you want you can but I don't think it is necessary Ack. I'll just leave it as is. -- To view, visit https://review.coreboot.org/c/coreboot/+/60995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Gerrit-Change-Number: 60995 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 09:31:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit January 2022