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Change subject: soc/intel/alderlake: Support more Alder Lake P IGD device IDs
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61441/comment/4d2a8181_90cd3cfb
PS5, Line 9: By checking doc 638514 and found some IGD device IDs are missed so
: that coreboot can't recognize and config it properly and causes gfx
: driver fails to init.
soc/intel/alderlake: Add Alder Lake P IGD device IDs
This patch adds additional IGD device IDs as per per document 638514.
BUG=b:216420554
TEST=coreboot is able to probe the IGD device during PCI enumeration.
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/61441/comment/75a41e84_bccf0551
PS5, Line 3906: #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_8 0x46b0
duplicate entry line #3899
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Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/skylake: Choose pcr write to disable HECI1
......................................................................
soc/intel/skylake: Choose pcr write to disable HECI1
Set the SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR config on Skylake
to perform heci1 disabling using pcr writes.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/finalize.c
2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61433/2
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Hello Reka Norman,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/61443
to review the following change.
Change subject: mb/google/brya: Add SPD configs for nivviks and nereid
......................................................................
mb/google/brya: Add SPD configs for nivviks and nereid
Add a mem_parts_used.txt for each of nivviks and nereid, containing the
memory parts used in their pre-proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.
nivviks:
Micron MT62F1G32D4DR-031 WT:B
nereid:
Samsung K3LKBKB0BM-MGCP
BUG=b:197479026
TEST=Build nivviks and nereid. Use cbfstool to check that coreboot.rom
contains an spd.bin.
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/nereid/memory/Makefile.inc
A src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
A src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
7 files changed, 53 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/61443/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index d8497b4..aa2ca25 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -60,6 +60,7 @@
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+ select MEMORY_SOLDERDOWN
select SOC_INTEL_ALDERLAKE_PCH_N
select SYSTEM_TYPE_LAPTOP
diff --git a/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc
new file mode 100644
index 0000000..f39c69a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 0(0b0000) Parts = K3LKBKB0BM-MGCP
diff --git a/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt
new file mode 100644
index 0000000..cce733c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
+
+DRAM Part Name ID to assign
+K3LKBKB0BM-MGCP 0 (0000)
diff --git a/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
new file mode 100644
index 0000000..c092a5f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+K3LKBKB0BM-MGCP
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
new file mode 100644
index 0000000..db35a4d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
new file mode 100644
index 0000000..1ad0e36
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
+
+DRAM Part Name ID to assign
+MT62F1G32D4DR-031 WT:B 0 (0000)
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9c853bd
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+MT62F1G32D4DR-031 WT:B
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Change subject: soc/intel/alderlake: Support more Alder Lake P IGD device IDs
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61441/comment/24116b36_e539c99d
PS3, Line 7: lake
> nit: Lake
Done.
Thanks. i added more IDs in 638514 in newer patchset just now.
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Change subject: soc/intel/alderlake: Support more Alder Lake P IGD device IDs
......................................................................
soc/intel/alderlake: Support more Alder Lake P IGD device IDs
By checking doc 638514 and found some IGD device IDs are missed so
that coreboot can't recognize and config it properly and causes gfx
driver fails to init.
Document Number: 638514
BUG=b:216420554
Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11
Signed-off-by: Kane Chen <kane.chen(a)intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/61441/5
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Change subject: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC
......................................................................
Patch Set 11: Code-Review+2
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Kane Chen, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Support more Alder lake P IGD device IDs
......................................................................
soc/intel/alderlake: Support more Alder lake P IGD device IDs
By checking doc 638514 and found some IGD device IDs are missed so
that coreboot can't recognize and config it properly and causes gfx
driver fails to init.
Document Number: 638514
BUG=b:216420554
Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11
Signed-off-by: Kane Chen <kane.chen(a)intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/61441/4
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Change subject: mb/google/brya: Add memory config for nissa
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/nissa/memory.c:
https://review.coreboot.org/c/coreboot/+/61439/comment/3ed69cc3_d8dadce1
PS1, Line 73: BOARD_TYPE_MOBILE
> Krishna, do you know how this should be set? I couldn't find any info on it.
You can look here, https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he…
We can leave it as Mobile I believe.
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