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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/herobrine/mainboard.c:
https://review.coreboot.org/c/coreboot/+/61342/comment/1c4080fc_b85889ec
PS2, Line 61: if (display_init_required()) {
> suspect code indent for conditional statements (8, 24)
Please fix.
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Change subject: qualcomm/sc7280: Add display external clock support in coreboot
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Patch Set 5: Code-Review+1
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61342/comment/28a98f96_e959e236
PS2, Line 9: BUG=b:182963902
Please add 216687885 to BUG list
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Change subject: qualcomm/sc7280: Add display external clock support in coreboot
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59611/comment/b8d2f986_868b2196
PS5, Line 13: BUG=b:182963902
Please add 216687885 to BUG list
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Change subject: mb/google/brya: Add memory config for nissa
......................................................................
Patch Set 1:
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File src/mainboard/google/brya/variants/baseboard/nissa/memory.c:
https://review.coreboot.org/c/coreboot/+/61439/comment/b8702355_df79d7fd
PS1, Line 21: ddr0
> Yes Reka. It is the duplication of the other channel.
Thanks
https://review.coreboot.org/c/coreboot/+/61439/comment/b19c42dc_c91cc718
PS1, Line 73: BOARD_TYPE_MOBILE
> I'm not sure about this.
Krishna, do you know how this should be set? I couldn't find any info on it.
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Change subject: mb/google/brya: Add memory config for nissa
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Patch Set 1:
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File src/mainboard/google/brya/variants/baseboard/nissa/memory.c:
https://review.coreboot.org/c/coreboot/+/61439/comment/8c2d24d9_4b343240
PS1, Line 21: ddr0
> A question for Intel - ddr0-3 don't exist on ADL-N. […]
Yes Reka. It is the duplication of the other channel.
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Change subject: mb/google/brya/var/taeko: Enable USB A port on DB
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61412/comment/8d99f1e8_5e9ab63c
PS1, Line 7: Enable USB A port on DB
> suggestion: […]
Updated in latest patch, thanks for the advice!
https://review.coreboot.org/c/coreboot/+/61412/comment/311b38e2_cbca3bde
PS1, Line 7: tarlo
> `taeko`
Done
https://review.coreboot.org/c/coreboot/+/61412/comment/e29b40f2_ffdac887
PS1, Line 9: Tarlo
> `Taeko`
Done
File src/mainboard/google/brya/variants/taeko/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/61412/comment/aa850b12_e73ca11a
PS1, Line 497: 7
> why 7? isn't 5 the next group #?
Modified the group to 5 in latest patch, thanks for the remind!
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Change subject: mb/google/brya/var/taeko: Enable USB A port on DB
......................................................................
mb/google/brya/var/taeko: Enable USB A port on DB
Add new FW_CONFIG option for DB_USB
BUG=b:216533764
TEST=emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: I1a43c256757f3fc4b53ba1f794587d6a00ba0aa5
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 22 insertions(+), 0 deletions(-)
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Change subject: soc/intel/alderlake: Support Alder lake IGD device id 0x4628
......................................................................
soc/intel/alderlake: Support Alder lake IGD device id 0x4628
IGD id 0x4628 is missed in pci_device_ids tables so that coreboot
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---
M src/include/device/pci_ids.h
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M src/soc/intel/common/block/graphics/graphics.c
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Change subject: soc/intel/alderlake: Support Alder lake IGD device id 0x4628
......................................................................
soc/intel/alderlake: Support Alder lake IGD device id 0x4628
IGD id 0x4628 is missed in pci_device_ids tables so that coreboot
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Document Number: 627270
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---
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