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Change subject: sc7280/qtiseclib blob update
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Patch Set 1:
(1 comment)
Patchset:
PS1:
Also, please add BUG=213636916 and TEST= fields to the commit message.
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Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
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Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6:
LGTM, but you should get final approval from someone at AMD.
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Change subject: src/lib: Added CBMEM tag id to parse ddr information
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Patch Set 16:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59194/comment/08256a7d_4e546c02
PS16, Line 9: BUG=b:182963902
Please add Bug id 177917361, to BUG=
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Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
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Patch Set 1:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/61352/comment/39a64193_3cbd53b1
PS1, Line 53: ext_pm_support
> > In addition, if no srcclk_pin is assigned, SRCK method will not be exported. […]
Yes. https://review.coreboot.org/c/coreboot/+/61354. the drive ACPI will call the exported method only if CondRefOf indicating the method exists.
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Change subject: sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2
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Patch Set 108:
(1 comment)
Patchset:
PS107:
> unresolve
Ok, seems like these patches haven't been updated to the suggestions in https://b.corp.google.com/issues/215605946#comment12.
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