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Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61353/comment/e3876ed0_0b44ff97
PS1, Line 9: -
> No need to indent.
ok
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/61353/comment/629d3912_4885bb12
PS1, Line 428: _ONS
> suggestion: […]
sure. I will make change.
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Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/61352/comment/b441d5a6_d638c233
PS1, Line 53: ext_pm_support
> Then there is still an invalid state; perhaps we can make an enumeration out of the legal combinatio […]
good point. I can add the enumeration.
In addition, if no srcclk_pin is assigned, SRCK method will not be exported. Also,PSD0 Method only exported for PCH root root. Do we also want to consider for overall? or should we add CondRefof in the device prior to calling these exported rtd3 methods for the cases that not all three methods are available from the root port?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61434 )
Change subject: util/lint: Remove SuperIO from checkpatch spellcheck
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61434/comment/1a4df301_bd72308f
PS1, Line 7: Remove
You replace it by the lowercase spelling?
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Change subject: sc7280/qtiseclib blob update
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/qc_blobs/+/61435/comment/f03229de_f3f6335e
PS1, Line 7: sc7280/qtiseclib blob update
Please follow the style by using a statement with a verb (in imperative mood). Also mention the version.
Patchset:
PS1:
Why do you rename the release notes, make the diff hard to review?
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61093 )
Change subject: soc/amd/sabrina: update PCI devices in devicetree.cb
......................................................................
soc/amd/sabrina: update PCI devices in devicetree.cb
Also update mb/amd/chausie accordingly.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/mainboard/amd/chausie/devicetree.cb
M src/soc/amd/sabrina/chipset.cb
2 files changed, 2 insertions(+), 13 deletions(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 0494f5b..98030f7 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -25,7 +25,6 @@
device domain 0 on
device ref iommu on end
- device ref gpp_gfx_bridge_0 on end # MXM
device ref gpp_bridge_0 on end # NVMe
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end # WWAN
diff --git a/src/soc/amd/sabrina/chipset.cb b/src/soc/amd/sabrina/chipset.cb
index 8c6fab9..caa78e1 100644
--- a/src/soc/amd/sabrina/chipset.cb
+++ b/src/soc/amd/sabrina/chipset.cb
@@ -7,10 +7,7 @@
device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end
- device pci 01.0 on end # Dummy Host Bridge, do not disable
- device pci 01.1 alias gpp_gfx_bridge_0 off end
- device pci 01.2 alias gpp_gfx_bridge_1 off end
- device pci 01.3 alias gpp_gfx_bridge_2 off end
+ device pci 01.0 on end # Dummy Host Bridge
device pci 02.0 on end # Dummy Host Bridge, do not disable
device pci 02.1 alias gpp_bridge_0 off end
@@ -19,7 +16,6 @@
device pci 02.4 alias gpp_bridge_3 off end
device pci 02.5 alias gpp_bridge_4 off end
device pci 02.6 alias gpp_bridge_5 off end
- device pci 02.7 alias gpp_bridge_6 off end
device pci 08.0 on end # Dummy Host Bridge, do not disable
device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
@@ -80,15 +76,9 @@
device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
end
- device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
- device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
- device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
- device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
- device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
- end
+ device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B
device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function
- device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio
end
device pci 14.0 alias smbus on end # primary FCH function
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61091 )
Change subject: soc/amd/sabrina/fsp_m_params: drop sata_enable UPD write
......................................................................
soc/amd/sabrina/fsp_m_params: drop sata_enable UPD write
There are no SATA controllers on the Sabrina SoC. The UPD field will be
removed later as a part of the initial UPD header update.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iedefd9f150e5bcb78173288e5fc9f1bbd6b498cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61091
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/sabrina/fsp_m_params.c
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
Fred Reitberger: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c
index abbb0d1..95d2d1e 100644
--- a/src/soc/amd/sabrina/fsp_m_params.c
+++ b/src/soc/amd/sabrina/fsp_m_params.c
@@ -148,7 +148,6 @@
mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda));
mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda));
- mcfg->sata_enable = is_dev_enabled(DEV_PTR(sata_0)) || is_dev_enabled(DEV_PTR(sata_1));
if (config->usb_phy_custom) {
mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy;
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61089 )
Change subject: soc/amd/sabrina/include/data_fabric: update IOMS0_FABRIC_ID
......................................................................
soc/amd/sabrina/include/data_fabric: update IOMS0_FABRIC_ID
The data fabric ID table in PPR #57243 Rev 1.50 has a different IOMS0
fabric ID than Cezanne.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I32890b5c03219f6ebf8180929d71ef726d382483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61089
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/sabrina/include/soc/data_fabric.h
1 file changed, 1 insertion(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
Fred Reitberger: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/sabrina/include/soc/data_fabric.h b/src/soc/amd/sabrina/include/soc/data_fabric.h
index 87db4d3e..fbae1c6 100644
--- a/src/soc/amd/sabrina/include/soc/data_fabric.h
+++ b/src/soc/amd/sabrina/include/soc/data_fabric.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Check if this is still correct */
-
#ifndef AMD_SABRINA_DATA_FABRIC_H
#define AMD_SABRINA_DATA_FABRIC_H
@@ -10,7 +8,7 @@
/* SoC-specific bits in D18F0_MMIO_CTRL0 */
#define DF_MMIO_NP BIT(16)
-#define IOMS0_FABRIC_ID 10
+#define IOMS0_FABRIC_ID 9
#define NUM_NB_MMIO_REGS 8
--
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