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Change subject: mb/google/herobrine: Add senor support QUP FW for I2C and SPI
......................................................................
Patch Set 12: Code-Review+2
(1 comment)
Patchset:
PS7:
> Ok, I see what you're doing now. You're just adding the senor board. […]
Done
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Change subject: sc7280/qtiseclib blob update
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi Saurabh,
Can you also please post the code changes in the qtiseclib repo as well?
Thanks!
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Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
......................................................................
Patch Set 2:
(10 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61354/comment/5f66b4a7_11f5b444
PS2, Line 10: when
> on
thanks
https://review.coreboot.org/c/coreboot/+/61354/comment/32d3c0be_43893b7a
PS2, Line 9: Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
: PXSX._RST is invoked when driver removal.
:
: Test:
: Add chip entry to the corresponding root port and check PXSX Device
: is generated in ssdt.
> Please do not indent.
sure
Patchset:
PS2:
> Thanks Cliff! […]
great. I will create a following CL to move MPTS to here.
File src/drivers/wwan/fm/acpi_fm350gl.c:
https://review.coreboot.org/c/coreboot/+/61354/comment/4652a58f_d69ce464
PS2, Line 29:
> Can you add a comment here about what FHRF does?
FHRF: first half reset flow and arg0. I will add the missing header.
https://review.coreboot.org/c/coreboot/+/61354/comment/9bd7d1ff_4a2107d9
PS2, Line 38: assert
> `deassert` […]
a bit lost here.... correct me if I am wrong. From rtd3 code. it uses acpigen_enable_tx_gpio to assert reset_gpio pin (i.e. PERST#, also active_low):
_off method:
/* Assert reset GPIO to place device into reset. */
if (config->reset_gpio.pin_count) {
acpigen_enable_tx_gpio(&config->reset_gpio);
From reading the GPIO value on DUT, acpigen_enable_tx_gpio drive '0' for active_low pin, which means asserting the pin. current code has been working fine for resetting the device, unless I miss a big part...
https://review.coreboot.org/c/coreboot/+/61354/comment/6dbacc53_d0e042ac
PS2, Line 42: assert
> `deassert` […]
same comment as earlier one.
https://review.coreboot.org/c/coreboot/+/61354/comment/e655da08_161601b1
PS2, Line 44: warm reset
> Arg0 == 0, means cold reset and […]
Arg0 = 0: warm reset.
Arg1 = 1: cold reset.
Let me add to comments.
https://review.coreboot.org/c/coreboot/+/61354/comment/948266d0_5cc4a7f5
PS2, Line 106: acpigen_write_store_int_to_namestr(1, acpi_device_path_join(parent_dev, "RTD3._OFS"));
> To ensure that these _ON and _OFF calls are properly paired, I would rather see these incremented an […]
ok. Let me change that.
https://review.coreboot.org/c/coreboot/+/61354/comment/9b2ee31d_7c71e1de
PS2, Line 106: acpi_device_path_join(parent_dev, "RTD3._OFS")
> nit: this is used twice, extract to a local variable
I will keep the last one.
https://review.coreboot.org/c/coreboot/+/61354/comment/38ef73a6_d152ff5a
PS2, Line 167: .read_resources = noop_read_resources,
: .set_resources = noop_set_resources,
: .acpi_fill_ssdt = wwan_fm350gl_acpi_fill_ssdt,
: .acpi_name = wwan_fm350gl_acpi_name,
: };
> nit: line these up like this (with tabs) […]
ok
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Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS1:
> Yes, since there isn't any metadata AFAIK, the name could be increased by somewhere in the range of […]
I was mistaken, building the cbfs image will fail if the -position isn't large enough to accommodate the cbfs_file struct, filename and metadata structs. I've updated the comments to make that clear
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61349
to look at the new patch set (#6).
Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image.
BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by CBFSPRINT during the build
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
---
M src/soc/amd/cezanne/Makefile.inc
1 file changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61349/6
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61094 )
Change subject: soc/amd/sabrina/chipset.cb: update USB ports
......................................................................
soc/amd/sabrina/chipset.cb: update USB ports
The corresponding mainboard design guide was used as a reference here.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/mainboard/amd/chausie/devicetree.cb
M src/soc/amd/sabrina/chipset.cb
2 files changed, 13 insertions(+), 39 deletions(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
Jason Glenesk: Looks good to me, but someone else must approve
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 98030f7..19815b3 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -41,20 +41,11 @@
device ref usb3_port0 on end
end
chip drivers/usb/acpi
- device ref usb3_port1 on end
- end
- chip drivers/usb/acpi
device ref usb2_port0 on end
end
chip drivers/usb/acpi
device ref usb2_port1 on end
end
- chip drivers/usb/acpi
- device ref usb2_port2 on end
- end
- chip drivers/usb/acpi
- device ref usb2_port3 on end
- end
end
end
end
@@ -62,23 +53,20 @@
chip drivers/usb/acpi
device ref xhci_1_root_hub on
chip drivers/usb/acpi
- device ref usb3_port4 on end
+ device ref usb3_port2 on end
end
chip drivers/usb/acpi
- device ref usb3_port5 on end
+ device ref usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port2 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port3 on end
end
chip drivers/usb/acpi
device ref usb2_port4 on end
end
- chip drivers/usb/acpi
- device ref usb2_port5 on end
- end
- chip drivers/usb/acpi
- device ref usb2_port6 on end
- end
- chip drivers/usb/acpi
- device ref usb2_port7 on end
- end
end
end
end
diff --git a/src/soc/amd/sabrina/chipset.cb b/src/soc/amd/sabrina/chipset.cb
index caa78e1..c477a17 100644
--- a/src/soc/amd/sabrina/chipset.cb
+++ b/src/soc/amd/sabrina/chipset.cb
@@ -1,5 +1,3 @@
-# TODO: Check if this is still correct
-
chip soc/amd/sabrina
device cpu_cluster 0 on
end
@@ -30,20 +28,11 @@
device usb 3.0 alias usb3_port0 off end
end
chip drivers/usb/acpi
- device usb 3.1 alias usb3_port1 off end
- end
- chip drivers/usb/acpi
device usb 2.0 alias usb2_port0 off end
end
chip drivers/usb/acpi
device usb 2.1 alias usb2_port1 off end
end
- chip drivers/usb/acpi
- device usb 2.2 alias usb2_port2 off end
- end
- chip drivers/usb/acpi
- device usb 2.3 alias usb2_port3 off end
- end
end
end
end
@@ -52,22 +41,19 @@
register "type" = "UPC_TYPE_HUB"
device usb 0.0 alias xhci_1_root_hub off
chip drivers/usb/acpi
- device usb 3.0 alias usb3_port4 off end
+ device usb 3.0 alias usb3_port2 off end
end
chip drivers/usb/acpi
- device usb 3.1 alias usb3_port5 off end
+ device usb 3.1 alias usb3_port3 off end
end
chip drivers/usb/acpi
- device usb 2.0 alias usb2_port4 off end
+ device usb 2.0 alias usb2_port2 off end
end
chip drivers/usb/acpi
- device usb 2.1 alias usb2_port5 off end
+ device usb 2.1 alias usb2_port3 off end
end
chip drivers/usb/acpi
- device usb 2.2 alias usb2_port6 off end
- end
- chip drivers/usb/acpi
- device usb 2.3 alias usb2_port7 off end
+ device usb 2.2 alias usb2_port4 off end
end
end
end
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61349
to look at the new patch set (#5).
Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image.
BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by CBFSPRINT during the build
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
---
M src/soc/amd/cezanne/Makefile.inc
1 file changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61349/5
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Change subject: soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZE
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/sabrina/chipset.cb: update USB ports
......................................................................
Patch Set 5: Code-Review+2
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