coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/purism/librem_skl: disable HECI PCI device
by Felix Held (Code Review) 28 Jan '22

28 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61408 ) Change subject: mb/purism/librem_skl: disable HECI PCI device ...................................................................... mb/purism/librem_skl: disable HECI PCI device As all librem_skl devices ship with the ME disabled via HAP bit and ME firmware "neutralized" via me_cleaner, the HECI1 PCI device should be marked off/disabled to ensure that heci_reset() is not called at the end of heci_init(), as this causes a 15s timeout delay when booting (introduced in commit cb2fd20 [soc/intel/common: Add HECI Reset flow in the CSE driver]). Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61408 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/purism/librem_skl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index ef898b2..94b79f9 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -160,7 +160,7 @@ device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 14.3 off end # Camera - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f Gerrit-Change-Number: 61408 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: psp_verstage: report developer mode to PSP
by Rob Barnes (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61369 ) Change subject: psp_verstage: report developer mode to PSP ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/psp_verstage/chipset.c: https://review.coreboot.org/c/coreboot/+/61369/comment/54f28c91_01995ecb PS1, Line 39: svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); When is CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE used? -- To view, visit https://review.coreboot.org/c/coreboot/+/61369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Gerrit-Change-Number: 61369 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:54:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: add new svc for cezanne
by Rob Barnes (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 ) Change subject: psp_verstage: add new svc for cezanne ...................................................................... Patch Set 1: (2 comments) File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h: https://review.coreboot.org/c/coreboot/+/61368/comment/1e00c1df_e4465518 PS1, Line 53: #define SVC_SET_PLATFORM_BOOT_MODE 0x6C nit: Why is 0x6B skipped? https://review.coreboot.org/c/coreboot/+/61368/comment/26c08f33_9dc6059b PS1, Line 144: CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check nit: I think CROS is more commonly used than CHROME_BOOK -- To view, visit https://review.coreboot.org/c/coreboot/+/61368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Gerrit-Change-Number: 61368 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:49:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
by Tim Wawrzynczak (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61126 ) Change subject: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/intel/alderlake/include/soc/pcr_ids.h: https://review.coreboot.org/c/coreboot/+/61126/comment/6bd2a235_49dddfde PS3, Line 35: : #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) : /* eMMC Port ID for Alder Lake N */ : #define PID_EMMC 0xa1 : #endif > nit: I don't know if we need the value guarded by an #if, we just have to make sure that only PCH-N […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Gerrit-Change-Number: 61126 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:46:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Drop stale TODO comment
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61454 ) Change subject: soc/intel/elkhartlake: Drop stale TODO comment ...................................................................... soc/intel/elkhartlake: Drop stale TODO comment This patch drops stale TODO comment about enabling eNEM on EHL. eNEM is non-POR on the elkhartlake product. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/61454/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 8604e12..a8d7618 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -22,7 +22,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Gerrit-Change-Number: 61454 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Choose SBI msg to disable HECI1
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61453 ) Change subject: soc/intel/elkhartlake: Choose SBI msg to disable HECI1 ...................................................................... soc/intel/elkhartlake: Choose SBI msg to disable HECI1 Select HECI_DISABLE_USING_SMM config on elkhartlake to perform heci1 disabling using SBI msg inside SMM (SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI). BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/61453/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index b829602..8604e12 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -46,6 +46,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA -- To view, visit https://review.coreboot.org/c/coreboot/+/61453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Gerrit-Change-Number: 61453 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in blobs[master]: 00730F01/binaryPI: fix firmware table lookup
by Marc Jones (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Michał Żygowski. Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/35969 ) Change subject: 00730F01/binaryPI: fix firmware table lookup ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/35969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I7d81998b34c24d8294c81631224d92133bb67f24 Gerrit-Change-Number: 35969 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:32:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/lint: Remove SuperIO from checkpatch spellcheck
by Paul Menzel (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61434 ) Change subject: util/lint: Remove SuperIO from checkpatch spellcheck ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I464305af539926ac8a45c9c0d59eeb2c78dea17a Gerrit-Change-Number: 61434 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:29:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0/include/fsp: fix fsp_header
by Paul Menzel (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Subrata Banik, Marshall Dawson, Tim Wawrzynczak, Name of user not set #1003801, Andrey Petrov, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58869 ) Change subject: drivers/intel/fsp2_0/include/fsp: fix fsp_header ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58869/comment/d7797aa0_37f9f8c7 PS8, Line 8: Please describe the problem (caused by unaligned FSP header). Does it fix a regression? -- To view, visit https://review.coreboot.org/c/coreboot/+/58869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646 Gerrit-Change-Number: 58869 Gerrit-PatchSet: 8 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add the Primary to Sideband bridge library
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Wonkyu Kim, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61283 ) Change subject: soc/intel/common: Add the Primary to Sideband bridge library ...................................................................... Patch Set 7: (2 comments) Patchset: PS5: > If no further comment, can we consider to move forward as baseline? I'm good with this Patchset: PS7: > Just question here. Before the FSP-S, p2sb is unhidden and FSP-S will hide that. So if before FSP-S, it hidden by coreboot. Will that causes some issue? As per my understanding, FSP will come and reenable it. No restriction with P2SB enable/disable prior to postboot_sai which is enforced by FSP-S. -- To view, visit https://review.coreboot.org/c/coreboot/+/61283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Gerrit-Change-Number: 61283 Gerrit-PatchSet: 7 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:27:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: John Zhao <john.zhao(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2022