coreboot-gerrit January 2022

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Change in coreboot[master]: IASL: Ignore IASL's "Missing dependency" warning
by Nico Huber (Code Review) 28 Jan '22

28 Jan '22

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59880 ) Change subject: IASL: Ignore IASL's "Missing dependency" warning ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Sorry, I was slow. What's the point of this? Doesn't it only move a warning from one place to another? (whilst losing infor- mation and adding complexity) -- To view, visit https://review.coreboot.org/c/coreboot/+/59880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28b437194f08232727623009372327fec15215dd Gerrit-Change-Number: 59880 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 18:32:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Choose PMC IPC to disable HECI1
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61458 ) Change subject: soc/intel/alderlake: Choose PMC IPC to disable HECI1 ...................................................................... soc/intel/alderlake: Choose PMC IPC to disable HECI1 This patch allows common CSE block to make HECI1 function disable using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config on alderlake to perform heci1 disabling using PMC IPC. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/smihandler.c 2 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61458/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 04e113a..1616029 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -76,6 +76,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 61fecdf..56814f5 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -16,9 +16,6 @@ */ void smihandler_soc_at_finalize(void) { - if (!CONFIG(HECI_DISABLE_USING_SMM)) - return; - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Gerrit-Change-Number: 61458 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Choose PMC IPC to disable HECI1
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61457 ) Change subject: soc/intel/tigerlake: Choose PMC IPC to disable HECI1 ...................................................................... soc/intel/tigerlake: Choose PMC IPC to disable HECI1 This patch allows common CSE block to make HECI1 function disable using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config on tigerlake to perform heci1 disabling using PMC IPC. Additionally, drop HECI_DISABLE_USING_SMM config from TGL SoC as heci1 disabling using PMC IPC can operate outside SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61457/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3ef1005..b9f53ce 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 @@ -82,7 +83,6 @@ select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM config MAX_CPUS int diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 843733f..5907e5c 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -16,7 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Gerrit-Change-Number: 61457 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Choose SBI msg to disable HECI1
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61456 to look at the new patch set (#2). Change subject: soc/intel/jasperlake: Choose SBI msg to disable HECI1 ...................................................................... soc/intel/jasperlake: Choose SBI msg to disable HECI1 Select HECI_DISABLE_USING_SMM config on jasperlake to perform heci1 disabling using SBI msg inside SMM (SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI). BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/61456/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 Gerrit-Change-Number: 61456 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Choose SBI msg to disable HECI1
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61456 ) Change subject: soc/intel/jasperlake: Choose SBI msg to disable HECI1 ...................................................................... soc/intel/jasperlake: Choose SBI msg to disable HECI1 Select HECI_DISABLE_USING_SMM config on jasperlake to perform heci1 disabling using SBI msg inside SMM (SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI). BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/smihandler.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/61456/1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 556b2f2..f516417 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -48,6 +48,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 3dca4a2..f2294fe 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -16,7 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 Gerrit-Change-Number: 61456 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Drop unnecessary guard for Heci1 disable UPD
by Subrata Banik (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61455 ) Change subject: soc/intel/cannonlake: Drop unnecessary guard for Heci1 disable UPD ...................................................................... soc/intel/cannonlake: Drop unnecessary guard for Heci1 disable UPD Add ability to disable Heci1 using FSP `Heci1Disabled` UPD. BUG=none TEST=Boot to OS, verify if Heci1 is disabled on hatch system using FSP when mainboard selects DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61455/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index af356d1..9a8a5ac 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -586,9 +586,8 @@ params->ScsUfsEnabled = is_devfn_enabled(PCH_DEVFN_UFS); params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3); -#if !CONFIG(HECI_DISABLE_USING_SMM) + /* Allow FSP to disable Heci1 */ params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); -#endif params->Device4Enable = config->Device4Enable; /* Teton Glacier hybrid storage support */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Gerrit-Change-Number: 61455 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/redrix: Enable MKBP wake
by Felix Held (Code Review) 28 Jan '22

28 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61383 ) Change subject: mb/google/brya/var/redrix: Enable MKBP wake ...................................................................... mb/google/brya/var/redrix: Enable MKBP wake To timely update stylus charging status (b:206012072), PCHG device events have been moved to MKBP. This patch registers the MKPB host event as a wake-up signal to match the change. EC filters other EC_MKBP_EVENT_* events (chromium:3413180). BUG=b:205675485,b:206012072 Cq-Depend: chromium:3413180 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: Ie4536b2c0ccc37f92dfa940c5a5712340a32c82c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61383 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/include/variant/ec.h 1 file changed, 8 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h index fa210e4..ea8fb54 100644 --- a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h @@ -5,42 +5,20 @@ #include <baseboard/ec.h> -#undef MAINBOARD_EC_SCI_EVENTS -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) -/* - * EC can wake from S3/S0ix with: - * 1. Lid open - * 2. AC Connect/Disconnect - * 3. Power button - * 4. Key press - * 5. Mode change - * 6. Host Device - */ #undef MAINBOARD_EC_S3_WAKE_EVENTS #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#undef MAINBOARD_EC_S0IX_WAKE_EVENTS +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT -- To view, visit https://review.coreboot.org/c/coreboot/+/61383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4536b2c0ccc37f92dfa940c5a5712340a32c82c Gerrit-Change-Number: 61383 Gerrit-PatchSet: 4 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/spd_cache.c: Drop comparison to {true, false}
by Felix Held (Code Review) 28 Jan '22

28 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61423 ) Change subject: lib/spd_cache.c: Drop comparison to {true, false} ...................................................................... lib/spd_cache.c: Drop comparison to {true, false} Change-Id: I0ef8c0159c99606aad537fd5e14d3c74e32651d8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61423 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/lib/spd_cache.c 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index be36141..44830a8 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -154,21 +154,21 @@ bool dimm_present_in_cache; bool dimm_changed = false; /* Check if the dimm is the same with last system boot. */ - for (i = 0; i < SC_SPD_NUMS && dimm_changed == false; i++) { + for (i = 0; i < SC_SPD_NUMS && !dimm_changed; i++) { /* Return true if any error happened here. */ if (get_spd_sn(blk->addr_map[i], &sn) == CB_ERR) return true; dimm_present_in_cache = get_cached_dimm_present(spd_cache, i); /* Dimm is not present now. */ if (sn == 0xffffffff) { - if (dimm_present_in_cache == false) + if (!dimm_present_in_cache) printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is not present\n", i); else { printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d lost\n", i); dimm_changed = true; } } else { /* Dimm is present now. */ - if (dimm_present_in_cache == true) { + if (dimm_present_in_cache) { if (memcmp(&sn, spd_cache + SC_SPD_OFFSET(i) + DDR4_SPD_SN_OFF, SPD_SN_LEN) == 0) printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is the same\n", @@ -195,7 +195,7 @@ /* Find the first present SPD */ for (i = 0; i < SC_SPD_NUMS; i++) - if (get_cached_dimm_present(spd_cache, i) == true) + if (get_cached_dimm_present(spd_cache, i)) break; if (i == SC_SPD_NUMS) { @@ -211,7 +211,7 @@ blk->len = SPD_PAGE_LEN; for (i = 0; i < SC_SPD_NUMS; i++) - if (get_cached_dimm_present(spd_cache, i) == true) + if (get_cached_dimm_present(spd_cache, i)) blk->spd_array[i] = spd_cache + SC_SPD_OFFSET(i); else blk->spd_array[i] = NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/61423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ef8c0159c99606aad537fd5e14d3c74e32651d8 Gerrit-Change-Number: 61423 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/spd_cache.c: Drop comparison to {true, false}
by Felix Held (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: HAOUAS Elyes. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61423 ) Change subject: lib/spd_cache.c: Drop comparison to {true, false} ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ef8c0159c99606aad537fd5e14d3c74e32651d8 Gerrit-Change-Number: 61423 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 28 Jan 2022 17:56:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/nb_acpi.c: Drop comparison to true
by Felix Held (Code Review) 28 Jan '22

28 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61422 ) Change subject: soc/intel/xeon_sp/nb_acpi.c: Drop comparison to true ...................................................................... soc/intel/xeon_sp/nb_acpi.c: Drop comparison to true Change-Id: Ib9670ee22e36dd988a75b2f8dc565534927b6107 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61422 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 9443966..bb98f0b 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -167,7 +167,7 @@ unsigned long atsr_size = 0; unsigned long pci_br_size = 0; - if (is_atsr == true && first && *first == true) { + if (is_atsr && first && *first) { printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " "PCI Segment Number: 0x%x\n", 0, pcie_seg); atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); -- To view, visit https://review.coreboot.org/c/coreboot/+/61422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9670ee22e36dd988a75b2f8dc565534927b6107 Gerrit-Change-Number: 61422 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2022