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Change subject: soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/alderlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/61127/comment/964e062f_86f00a2f
PS4, Line 42: // Sleep 50 us
:
: PGEN = 0 // Disable PG
nit: use consistent comment style, e,.g. `/* */`
https://review.coreboot.org/c/coreboot/+/61127/comment/bc0ff8c8_a132613b
PS4, Line 55: // Enable PG
nit: use consistent comment style, e,.g. `/* */`
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Change subject: soc/intel/elkhartlake: Drop stale TODO comment
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
thanks Subrata!
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Change subject: soc/intel/elkhartlake: Choose SBI msg to disable HECI1
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61453/comment/b09accd2_287e3be6
PS2, Line 7: Choose
nit: Use
https://review.coreboot.org/c/coreboot/+/61453/comment/835d0d71_f723a3fb
PS2, Line 9: Select HECI_DISABLE_USING_SMM config on elkhartlake to perform heci1
: disabling using SBI msg inside SMM
nit: Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable heci1 using the SBI msg in SMM.
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Change subject: soc/intel/cannonlake: Choose SBI msg to disable HECI1
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61451/comment/19b7ae1e_54ce61ee
PS3, Line 9: on Cannonlake to perform heci1
: disabling using SBI msg inside SMM
> nit: for Cannon Lake to disable HECI1 device using the SBI message in SMI mode
SMI => System Management Interrupt
SMM => System Management Mode
SMI is the trigger point to enter into SMM, hence, there is nothing called SMI mode IMO.
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Change subject: soc/intel/cannonlake: Choose SBI msg to disable HECI1
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61451/comment/975c5267_67198d9b
PS3, Line 7: Choose
nit:Use?
https://review.coreboot.org/c/coreboot/+/61451/comment/9ef7b583_df32c86d
PS3, Line 9: on Cannonlake to perform heci1
: disabling using SBI msg inside SMM
nit: for Cannon Lake to disable HECI1 device using the SBI message in SMI mode
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Lean Sheng Tan, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs
......................................................................
soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs
Lists of changes:
- SoC selects `SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY` Kconfig
to skip FSP notify APIs (Ready to boot and End of Firmware)
and make useof native coreboot driver to perform require heci
notify prior booting to OS.
- Implement SoC overrides to set D0I3 for all Heci devices.
BUG=b:211954778
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0198c9568de0e74053775682a44324405746389a
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
2 files changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/60406/10
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#15).
Change subject: soc/intel/common/cse: Implement HECI notify
......................................................................
soc/intel/common/cse: Implement HECI notify
This patch implements the required HECI operations to perform prior
to booting to OS after platform decides to skip FSP notify APIs
i.e. Ready to Boot and End Of Firmware.
Additionally, creates helper function to set D0I3 for all HECI devices.
SoC code to implement the function `soc_heci_set_d0i3` while putting
the entire HECI device lists into D0i3.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY:
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 73 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/15
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Change subject: soc/intel/common/cse: Rework heci_disable function
......................................................................
soc/intel/common/cse: Rework heci_disable function
This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the
compilation failure.
Finally, rename heci_disable() function to heci1_disable() to make it
more meaningful.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
---
M src/soc/intel/alderlake/smihandler.c
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/disable_heci.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/elkhartlake/smihandler.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/jasperlake/smihandler.c
M src/soc/intel/skylake/include/soc/pcr_ids.h
M src/soc/intel/tigerlake/smihandler.c
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
13 files changed, 94 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/6
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