coreboot-gerrit September 2021

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Change in coreboot[master]: mb/intel/adlrvp_p: Enable TCSS USB ports device path
by Paul Menzel (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Maulik V Vaghela, Meera Ravindranath, Sridhar Siricilla, Bernardo Perez Priego, Tim Wawrzynczak, Deepti Deshatty. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57274 ) Change subject: mb/intel/adlrvp_p: Enable TCSS USB ports device path ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57274/comment/c9d4d297_2fcb3b69 PS2, Line 8: So there are exactly four ports? -- To view, visit https://review.coreboot.org/c/coreboot/+/57274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadc0df2e6e29a5afbcbb7db1ae0be6546dbcdc1a Gerrit-Change-Number: 57274 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Mon, 06 Sep 2021 21:31:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM
by Paul Menzel (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Meera Ravindranath, Tim Wawrzynczak, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57411 ) Change subject: mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57411/comment/10beae9e_2ad81dc7 PS1, Line 14: TEST=Boot adlrvp to OS, ensure no TPM errors. What is the exact error? -- To view, visit https://review.coreboot.org/c/coreboot/+/57411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Gerrit-Change-Number: 57411 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 06 Sep 2021 21:20:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google: Add OEM product names for various boards
by Paul Menzel (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57392 ) Change subject: mb/google: Add OEM product names for various boards ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Gerrit-Change-Number: 57392 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 06 Sep 2021 21:19:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo: Use pci_and_config32
by 9elements QA (Code Review) 06 Sep '21

06 Sep '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55606 ) Change subject: mb/lenovo: Use pci_and_config32 ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 1 / 13 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/76346 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/76345 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/76344 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/76343 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/76342 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/76341 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/76340 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/76339 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/76338 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/76337 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/76336 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/76335 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/76334 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/55606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I082d31d59660c48065f9390975817d3ed553da2d Gerrit-Change-Number: 55606 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Sep 2021 21:01:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0/Kconfig: select HAVE_DISPLAY_MTRRS
by Nico Huber (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Raul Rangel, Martin Roth, Furquan Shaikh, Marshall Dawson, Angel Pons, Andrey Petrov, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51575 ) Change subject: drivers/intel/fsp2_0/Kconfig: select HAVE_DISPLAY_MTRRS ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19 Gerrit-Change-Number: 51575 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Sep 2021 20:49:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google: Add board name comments for each board
by Felix Held (Code Review) 06 Sep '21

06 Sep '21

Attention is currently required from: Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57390 ) Change subject: mb/google: Add board name comments for each board ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib941318842136212727f56fc6130381c5c9cd55b Gerrit-Change-Number: 57390 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 06 Sep 2021 20:04:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selected
by Felix Held (Code Review) 06 Sep '21

06 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57368 ) Change subject: drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selected ...................................................................... drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selected Platforms that rely on the FSP for parts of the hardware initialization likely won't boot successfully when no FSP binaries are added during the build, so print a warning at the end of the build in this case. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Suggested-by: Martin Roth <martinroth(a)google.com> Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57368 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 80dc93b..01b4c9e 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -110,8 +110,17 @@ ifeq ($(call strip_quotes,$(CONFIG_FSP_S_FILE)),) $(error No FSP-S binary file specified.) endif # CONFIG_FSP_S_FILE +else # CONFIG_ADD_FSP_BINARIES +build_complete:: warn_no_fsp_binaries endif # CONFIG_ADD_FSP_BINARIES +PHONY+=warn_no_fsp_binaries +warn_no_fsp_binaries: + printf "\n\t** WARNING **\n" + printf "ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP.\n" + printf "The resulting image won't contain the FSP binaries and will not boot unless\n" + printf "they are added later.\n" + subdirs-y += ppi endif -- To view, visit https://review.coreboot.org/c/coreboot/+/57368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6 Gerrit-Change-Number: 57368 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: autoport: search for the HDA device on PCH
by Iru Cai (vimacs) (Code Review) 06 Sep '21

06 Sep '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34357 to review the following change. Change subject: autoport: search for the HDA device on PCH ...................................................................... autoport: search for the HDA device on PCH Haswell has its Mini-HD device and is at card0, so we need to search for the PCH HD Audio device instead of using card0. Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/log_maker.go 1 file changed, 53 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34357/1 diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go index 08b35d2..2a524d3 100644 --- a/util/autoport/log_maker.go +++ b/util/autoport/log_maker.go @@ -9,6 +9,7 @@ "os" "os/exec" "strings" + "bytes" ) func TryRunAndSave(output string, name string, arg []string) error { @@ -74,6 +75,44 @@ return } +func MakeHDALogs(outDir string, cardName string) { + SysDir := "/sys/class/sound/" + cardName + "/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/" + cardName + "/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } +} + func MakeLogs(outDir string) { os.MkdirAll(outDir, 0700) RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") @@ -97,40 +136,23 @@ RunAndSave(outDir+"/ectool.log", "../ectool/ectool", "-pd") RunAndSave(outDir+"/superiotool.log", "../superiotool/superiotool", "-ade") - SysDir := "/sys/class/sound/card0/" - files, _ := ioutil.ReadDir(SysDir) - for _, f := range files { - if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { - in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") - defer in.Close() - if err != nil { - log.Fatal(err) + SysSound := "/sys/class/sound/" + card := "" + cards, _ := ioutil.ReadDir(SysSound) + for _, f := range cards { + if strings.HasPrefix(f.Name(), "card") { + cid, err := ioutil.ReadFile(SysSound + f.Name() + "/id") + if err == nil && bytes.Equal(cid, []byte("PCH\n")) { + fmt.Fprintln(os.Stderr, "PCH sound card is", f.Name()) + card = f.Name() } - out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) - if err != nil { - log.Fatal(err) - } - defer out.Close() - io.Copy(out, in) } } - ProcDir := "/proc/asound/card0/" - files, _ = ioutil.ReadDir(ProcDir) - for _, f := range files { - if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { - in, err := os.Open(ProcDir + f.Name()) - defer in.Close() - if err != nil { - log.Fatal(err) - } - out, err := os.Create(outDir + "/" + f.Name()) - if err != nil { - log.Fatal(err) - } - defer out.Close() - io.Copy(out, in) - } + if card != "" { + MakeHDALogs(outDir, card) + } else { + fmt.Fprintln(os.Stderr, "HDAudio not found on PCH.") } for _, fname := range []string{"cpuinfo", "ioports"} { @@ -154,7 +176,7 @@ defer out.Close() ClassInputDir := "/sys/class/input/" - files, _ = ioutil.ReadDir(ClassInputDir) + files, _ := ioutil.ReadDir(ClassInputDir) for _, f := range files { if strings.HasPrefix(f.Name(), "input") && !f.Mode().IsRegular() { /* Allow both dirs and symlinks. */ in, err := os.Open(ClassInputDir + f.Name() + "/id/bustype") -- To view, visit https://review.coreboot.org/c/coreboot/+/34357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4 Gerrit-Change-Number: 34357 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: inteltool: Support dumping IOBP register values
by Iru Cai (vimacs) (Code Review) 06 Sep '21

06 Sep '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41473 to review the following change. Change subject: inteltool: Support dumping IOBP register values ...................................................................... inteltool: Support dumping IOBP register values Currently only LynxPoint IOBP registers are added. The SATA IOBP registers are found in coreboot sb/intel/lynxpoint, and the USB IOBP registers are found in mrc.bin. Tested with Dell Latitude E7240, which fails to read SATA_IOBP_SP*G3IR (does LynxPoint really use them?) and reads other IOBP registers successfully. Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/inteltool/Makefile M util/inteltool/inteltool.h A util/inteltool/iobp.c M util/inteltool/rootcmplx.c 4 files changed, 153 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/41473/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 1ae04d4..3b692fd 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -16,7 +16,7 @@ OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o lpc.o + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o lpc.o iobp.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index b314fe4..6c361b4 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -386,6 +386,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_lpc(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); +void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba); int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb, size_t* community_count, diff --git a/util/inteltool/iobp.c b/util/inteltool/iobp.c new file mode 100644 index 0000000..dafcb00 --- /dev/null +++ b/util/inteltool/iobp.c @@ -0,0 +1,149 @@ +/* inteltool - dump all registers on an Intel CPU + chipset based system */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdio.h> +#include <stdlib.h> +#include "inteltool.h" + +#define RCBA8(x) (*((volatile u8 *)(rcba + x))) +#define RCBA16(x) (*((volatile u16 *)(rcba + x))) +#define RCBA32(x) (*((volatile u32 *)(rcba + x))) +#define RCBA64(x) (*((volatile u64 *)(rcba + x))) +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_READY 0x0001 +#define IOBPS_TX_MASK 0x0006 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 +#define IOBPS_WRITE 0x0700 +#define IOBPU 0x233a +#define IOBPU_MAGIC 0xf000 + +#define IOBP_RETRY 1000 +static inline int iobp_poll(volatile uint8_t *rcba) +{ + for (int try = IOBP_RETRY; try > 0; try --) { + u16 status = RCBA16(IOBPS); + if ((status & IOBPS_READY) == 0) + return 1; + // udelay(10); + } + + printf("IOBP: timeout waiting for transaction to complete\n"); + return 0; +} + +static u32 pch_iobp_read(volatile uint8_t *rcba, u32 address) +{ + u16 status; + + if (!iobp_poll(rcba)) + return 0; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_READ; + RCBA16(IOBPS) = status; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll(rcba)) + return 0; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printf("IOBP: read 0x%08x failed\n", address); + return 0; + } + + /* Read IOBP data */ + return RCBA32(IOBPD); +} + +typedef struct { + u32 addr; + char *name; +} iobp_register_t; + +static const iobp_register_t lynxpoint_iobp_registers[] = { + /* SATA IOBP */ + {0xea000151, "SATA_IOBP_SP0G3IR"}, + {0xea000051, "SATA_IOBP_SP1G3IR"}, + {0xea002550, "SATA_IOBP_SP0DTLE_DATA"}, + {0xea002554, "SATA_IOBP_SP0DTLE_EDGE"}, + {0xea002750, "SATA_IOBP_SP1DTLE_DATA"}, + {0xea002754, "SATA_IOBP_SP1DTLE_EDGE"}, + /* USB port IOBP */ + {0xe5004100, "USBP01"}, + {0xe5004200, "USBP02"}, + {0xe5004300, "USBP03"}, + {0xe5004400, "USBP04"}, + {0xe5004500, "USBP05"}, + {0xe5004600, "USBP06"}, + {0xe5004700, "USBP07"}, + {0xe5004800, "USBP08"}, + /* LynxPoint-LP doesn't have port 9-14, the IOBP values are zero */ + {0xe5004900, "USBP09"}, + {0xe5004a00, "USBP10"}, + {0xe5004b00, "USBP11"}, + {0xe5004c00, "USBP12"}, + {0xe5004d00, "USBP13"}, + {0xe5004e00, "USBP14"}, +}; + +void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba) +{ + const iobp_register_t *iobp_registers = NULL; + size_t iobp_size = 0; + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_C8_MOBILE: + case PCI_DEVICE_ID_INTEL_C8_DESKTOP: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: + iobp_registers = lynxpoint_iobp_registers; + iobp_size = ARRAY_SIZE(lynxpoint_iobp_registers); + break; + default: + break; + } + + if (iobp_size == 0) + return; + + printf("\n============= IOBP ==============\n\n"); + + for (size_t i = 0; i < iobp_size; i++) { + u32 address = iobp_registers[i].addr; + const char *name = iobp_registers[i].name; + u32 v = pch_iobp_read(rcba, address); + printf("0x%08x: 0x%08x (%s)\n", address, v, name); + } +} diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 490897f..9819af5 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -138,6 +138,8 @@ printf("0x%04x: 0x%08x\n", i, read32(rcba + i)); } + print_iobp(sb, rcba); + unmap_physical((void *)rcba, size); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9 Gerrit-Change-Number: 41473 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

4 22

Change in coreboot[master]: Update vboot submodule to upstream main
by Felix Held (Code Review) 06 Sep '21

06 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57322 ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id ccc56f4: vboot: add x86 SHA256 ext support to commit id 4423276: crossystem: add a hwid override mechanism from chromeos-config Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> Change-Id: I7bd73b9f6c0492f96c336b61e21ecae37b8f3606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57322 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Thejaswani Putta <thejaswani.putta(a)intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Thejaswani Putta: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index ccc56f4..4423276 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit ccc56f46c51fa9d0c2b3c086ace97c14fe887c32 +Subproject commit 4423276b4607cf1b3975eaff57d17869c0620ecd -- To view, visit https://review.coreboot.org/c/coreboot/+/57322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bd73b9f6c0492f96c336b61e21ecae37b8f3606 Gerrit-Change-Number: 57322 Gerrit-PatchSet: 2 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit September 2021