coreboot-gerrit August 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede: Create corori variant
by Karthik Ramasubramanian (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Ian Feng, Henry Sun, Aseda Aboagye. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56796 ) Change subject: mb/google/dedede: Create corori variant ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/dedede/variants/corori/overridetree.cb: https://review.coreboot.org/c/coreboot/+/56796/comment/083bdec7_d8bb7bff PS2, Line 37: end # PCH eSPI Turn off GSPI 0 to CR50. device pci 1e.2 off end # GSPI 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/56796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Gerrit-Change-Number: 56796 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Comment-Date: Thu, 05 Aug 2021 18:57:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/variants/haboki: add discrete TPM in overridetree
by Karthik Ramasubramanian (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Henry Sun, Chen Wisley, Aseda Aboagye, Wisley Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56829 ) Change subject: mb/google/dedede/variants/haboki: add discrete TPM in overridetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08f2a562c3f62c60402350151ea260b70890a744 Gerrit-Change-Number: 56829 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Aug 2021 18:50:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codec
by Karthik Ramasubramanian (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Sunwei Li, Henry Sun, Weimin Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56795 ) Change subject: mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codec ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/dedede/variants/cappy2/gpio.c: https://review.coreboot.org/c/coreboot/+/56795/comment/07afad10_de9e014b PS6, Line 25: PAD_NC(GPP_D18, NONE), What is in D18? https://review.coreboot.org/c/coreboot/+/56795/comment/8f685e7c_f6c1c8c2 PS6, Line 36: BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); I believe the change here works well with CB:56616 i.e. both the changes are taking effect. -- To view, visit https://review.coreboot.org/c/coreboot/+/56795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9121e75eaf46b43e6dc5ef2e31029a153c7a807d Gerrit-Change-Number: 56795 Gerrit-PatchSet: 6 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Aug 2021 18:45:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add MMIO support in PCI lib
by Prasad Malisetty (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Shelley Chen, Ravi kumar, Furquan Shaikh, Paul Menzel, Julius Werner, mturney mturney. Prasad Malisetty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53903 ) Change subject: libpayload: Add MMIO support in PCI lib ...................................................................... Patch Set 29: (3 comments) File payloads/libpayload/drivers/pci.c: https://review.coreboot.org/c/coreboot/+/53903/comment/6f09c160_30bac237 PS22, Line 35: #if CONFIG(LP_MMCONF_SUPPORT) : void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + reg; : return read8(cfg_addr); : #endif : outl(device | (reg & ~3), 0xCF8); : return inb(0xCFC + (reg & 3)); > Just checked patchset#28. I don't think we need to duplicate the entire pci.c file. […] Hi Furquan, Thanks for the review. I have few questions on above context. Below API's are already present in pci.c file. pci_io_read_config8 pci_io_write_config8 pci_io_read_config16 pci_io_write_config16 pci_io_read_config32 pci_io_write_config32 are you referring "pci_read/write_config8/16/32" in pci.c file ? As you mentioned,adding new Kconfig for IO and MMIO. We can add PCI_IO_OPS Kconfig which is default and select for arch_X86. And new MMIO ops which are added newly in pci_ops.c (patch #28) will be added to the build when MMIO_BASE_ADDRESS is present Is my analysis is right on above comment ? Please let me know, I will incorporate the changes in next version patch. Thanks -Prasad File payloads/libpayload/drivers/pci_ops.c: https://review.coreboot.org/c/coreboot/+/53903/comment/b2ab93dd_f1749039 PS28, Line 37: u32 devfn = ((dev >> 3) & 0x1f) | (dev & 0x07); > I think we are probably going to need separate map functions to map (bus,dev,fn) to the format expec […] Hi Furquan, Yes, QC platform required to configure the ATU to access the config space. In Coreboot PCIe root complex driver, after device enumeration is done we are configuring the ATU for device config access. we will add the same mapping format which we are using in CB PCIe driver. will validate and incorporate the change in next version. Thanks -Prasad File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/53903/comment/4c332d79_da674d4b PS22, Line 90: > Not yet addressed. Hi Furquan, I missed it in patch 28 version. Will resolve and incorporate the change in next version. -- To view, visit https://review.coreboot.org/c/coreboot/+/53903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Gerrit-Change-Number: 53903 Gerrit-PatchSet: 29 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 05 Aug 2021 18:35:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/pcengines/apu2: add and use IOMUX defines
by Felix Held (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Michał Żygowski, Piotr Król. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56836 ) Change subject: mb/pcengines/apu2: add and use IOMUX defines ...................................................................... mb/pcengines/apu2: add and use IOMUX defines Add GPIO IOMUX defines for the pins that are used in the mainboard code which enables using the PAD_GPI and PAD_GPO macros. TEST=Timeless build for APU2/3/4/5 results in identical binary. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7 --- M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/pcengines/apu2/romstage.c 2 files changed, 30 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/56836/1 diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 6386220..fb4edd9 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -26,4 +26,18 @@ #define GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) #define GPIO_71 0x4D // PROCHOT +#define GPIO_22_IOMUX_GPIOxx 0 +#define GPIO_32_IOMUX_GPIOxx 0 +#define GPIO_33_IOMUX_GPIOxx 0 +#define GPIO_49_IOMUX_GPIOxx 2 +#define GPIO_50_IOMUX_GPIOxx 2 +#define GPIO_51_IOMUX_GPIOxx 2 +#define GPIO_55_IOMUX_GPIOxx 3 +#define GPIO_57_IOMUX_GPIOxx 1 +#define GPIO_58_IOMUX_GPIOxx 1 +#define GPIO_59_IOMUX_GPIOxx 3 +#define GPIO_64_IOMUX_GPIOxx 2 +#define GPIO_68_IOMUX_GPIOxx 0 +#define GPIO_71_IOMUX_GPIOxx 0 + #endif /* GPIO_FTNS_H */ diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 9b1435a..7cfa415 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -31,39 +31,31 @@ } const struct soc_amd_gpio gpio_common[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_49, Function2, PAD_PULL(PULL_NONE)), - PAD_CFG_STRUCT(GPIO_50, Function2, PAD_PULL(PULL_NONE)), - PAD_CFG_STRUCT(GPIO_71, Function0, PAD_PULL(PULL_NONE)), - /* Output enabled, value low, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_57, Function1, PAD_OUTPUT(LOW)), - PAD_CFG_STRUCT(GPIO_58, Function1, PAD_OUTPUT(LOW)), - PAD_CFG_STRUCT(GPIO_59, Function3, PAD_OUTPUT(LOW)), - /* Output enabled, value high, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_51, Function2, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_55, Function3, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_64, Function2, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_68, Function0, PAD_OUTPUT(HIGH)), + PAD_GPI(GPIO_49, PULL_NONE), + PAD_GPI(GPIO_50, PULL_NONE), + PAD_GPI(GPIO_71, PULL_NONE), + PAD_GPO(GPIO_57, LOW), + PAD_GPO(GPIO_58, LOW), + PAD_GPO(GPIO_59, LOW), + PAD_GPO(GPIO_51, HIGH), + PAD_GPO(GPIO_55, HIGH), + PAD_GPO(GPIO_64, HIGH), + PAD_GPO(GPIO_68, HIGH), }; const struct soc_amd_gpio gpio_apu2[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)), + PAD_GPI(GPIO_32,PULL_NONE), }; const struct soc_amd_gpio gpio_apu34[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)), - /* Output enabled, value low, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(LOW)), + PAD_GPI(GPIO_32, PULL_NONE), + PAD_GPO(GPIO_33, LOW), }; const struct soc_amd_gpio gpio_apu5[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_22, Function0, PAD_PULL(PULL_NONE)), - /* Output enabled, value high, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_32, Function0, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(HIGH)), + PAD_GPI(GPIO_22, PULL_NONE), + PAD_GPO(GPIO_32, HIGH), + PAD_GPO(GPIO_33, HIGH), }; static void early_lpc_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/56836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7 Gerrit-Change-Number: 56836 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] soc/amd/cezanne/include/gpio: add remote GPIO pin mux defini...
by Felix Held (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56811 to look at the new patch set (#7). Change subject: [TESTME] soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitions ...................................................................... [TESTME] soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitions Add the pin definitions for the remote GPIOs and the GPIO pin mux values for the GPIO mode of those pins. For now, accessing the remote GPIOs is only supported from the native coreboot code running on the x86 cores and not from verstage on PSP or ACPI. TODO: Test the code. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb --- M src/soc/amd/cezanne/include/soc/gpio.h 1 file changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/56811/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb Gerrit-Change-Number: 56811 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7180: Cleanups for drivers with common clock
by build bot (Jenkins) (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Shelley Chen, Ravi kumar, Taniya Das, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56587 ) Change subject: qualcomm/sc7180: Cleanups for drivers with common clock ...................................................................... Patch Set 4: (1 comment) File src/soc/qualcomm/sc7180/clock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125768): https://review.coreboot.org/c/coreboot/+/56587/comment/adcdcc6e_2bb0e601 PS4, Line 347: * Update half_divider passed from display, this is to accomodate 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/56587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Gerrit-Change-Number: 56587 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 05 Aug 2021 18:13:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7180: Cleanups for drivers with common clock
by mturney mturney (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Shelley Chen, Ravi kumar, Taniya Das, mturney mturney. mturney mturney has uploaded a new patch set (#4) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/56587 ) Change subject: qualcomm/sc7180: Cleanups for drivers with common clock ...................................................................... qualcomm/sc7180: Cleanups for drivers with common clock As we move to use the common clock driver, the sc7180 clock driver, watchdog and display drivers requires few cleanups, thus update the impacted drivers. Earlier the display client is expected to provide 2n divider value, as the divider value in register is in form "2n-1". mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; The older convention in the upcoming patches would be replaced with the common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated. mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0; To accommodate impacting the functionality, the half_divider is taken care in the clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/display/dsi_phy.c M src/soc/qualcomm/sc7180/include/soc/clock.h M src/soc/qualcomm/sc7180/watchdog.c 4 files changed, 65 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/56587/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Gerrit-Change-Number: 56587 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: clock: Add support for common clock driver
by mturney mturney (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. mturney mturney has uploaded a new patch set (#3) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/56588 ) Change subject: soc/qualcomm/common: clock: Add support for common clock driver ...................................................................... soc/qualcomm/common: clock: Add support for common clock driver The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- A src/soc/qualcomm/common/clock.c A src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 5 files changed, 504 insertions(+), 367 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56588/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Gerrit-Change-Number: 56588 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7280: Move to use common clock driver for sc7280
by mturney mturney (Code Review) 05 Aug '21

05 Aug '21

Attention is currently required from: Ravi kumar, Taniya Das, Paul Menzel, mturney mturney. mturney mturney has uploaded a new patch set (#58) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50580 ) Change subject: qualcomm/sc7280: Move to use common clock driver for sc7280 ...................................................................... qualcomm/sc7280: Move to use common clock driver for sc7280 It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. Also add support for Zonda PLL enable for CPU in common clock driver. Refactor the SC7280 clock driver to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/clock.h 6 files changed, 915 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50580/58 -- To view, visit https://review.coreboot.org/c/coreboot/+/50580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Gerrit-Change-Number: 50580 Gerrit-PatchSet: 58 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2021