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Change subject: [TESTME] mb/amd/majolica/Kconfig: add EFS SPI settings
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Patch Set 1: Code-Review+1
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Change subject: mb/google/guybrush: Switch from 33MHz to 66MHz SPI Speed
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Patch Set 3: Code-Review+2
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Change subject: mb/pcengines/apu2: add and use IOMUX defines
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Patch Set 1:
(1 comment)
File src/mainboard/pcengines/apu2/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125811):
https://review.coreboot.org/c/coreboot/+/56836/comment/852a2b42_c978fa68
PS1, Line 47: PAD_GPI(GPIO_32,PULL_NONE),
space required after that ',' (ctx:VxV)
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Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
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Patch Set 63:
(2 comments)
File src/drivers/spi/spi_flash.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125804):
https://review.coreboot.org/c/coreboot/+/50586/comment/b42f4bde_39952965
PS63, Line 541: while (1)
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Change subject: mb/google/dedede: Create driblee variant
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Patch Set 2:
(2 comments)
File src/mainboard/google/dedede/variants/driblee/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/56798/comment/8e0bfde6_592eaec4
PS2, Line 30:
register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0
register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
https://review.coreboot.org/c/coreboot/+/56798/comment/6b7b78c9_dca1883f
PS2, Line 37: end # PCH eSPI
Disable GSPI0 device to CR50.
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Change subject: mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot
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Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56826/comment/a18b950b_8dfedc34
PS2, Line 9: Keep the clock source for PCIe slots as always on. Also turn off the
maybe specify that the clock sources for the PCIe slots are 3 and 4?
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