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Change subject: soc/intel/broadwell: Refactor getting EM4/EM5 values
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Change subject: soc/intel/broadwell: Drop unused `cdclk` chip field
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Change subject: soc/intel/broadwell: Rename remaining `igd` to `gma`
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Change subject: nb/intel/haswell: Program Mini-HD EM4 and EM5 registers
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Change subject: nb/intel/haswell/gma.c: Refactor CdClk init code
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Patch Set 3: Code-Review+1
(1 comment)
File src/northbridge/intel/haswell/gma.c:
https://review.coreboot.org/c/coreboot/+/50136/comment/3ca78125_2b8b66ff
PS3, Line 369: * ULX defaults to 337MHz with possible override for 450MHz
: * ULT is fixed at 450MHz
: * others default to 540MHz with possible override for 450MHz
The indentation and alingment looks strange to me.
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Change subject: nb/intel/haswell/gma.c: Add ULX PCI device IDs
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Patch Set 3: Code-Review+2
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