coreboot-gerrit August 2021

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Change in coreboot[master]: mb/google/dedede: Create bugzzy variant
by Teddy Shih (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Henry Sun, Edward Doan, Karthik Ramasubramanian. Teddy Shih has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56716 ) Change subject: mb/google/dedede: Create bugzzy variant ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Dear All, Thank you for your review. Best Regards, Teddy -- To view, visit https://review.coreboot.org/c/coreboot/+/56716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1eefe80831f96b167e920e84bb7804e45e91d1 Gerrit-Change-Number: 56716 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 02 Aug 2021 05:50:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Create bugzzy variant
by Teddy Shih (Code Review) 02 Aug '21

02 Aug '21

Teddy Shih has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56716 ) Change subject: mb/google/dedede: Create bugzzy variant ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Dear All, Thank you for your review. Best Regards, Teddy -- To view, visit https://review.coreboot.org/c/coreboot/+/56716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1eefe80831f96b167e920e84bb7804e45e91d1 Gerrit-Change-Number: 56716 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Aug 2021 05:38:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taeko: Configure GPIOs according to schematics
by build bot (Jenkins) (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Tim Wawrzynczak, YH Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56754 ) Change subject: mb/google/brya/variants/taeko: Configure GPIOs according to schematics ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/taeko/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125521): https://review.coreboot.org/c/coreboot/+/56754/comment/08fc579c_8b93b1d5 PS2, Line 219: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/56754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Gerrit-Change-Number: 56754 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Aug 2021 05:34:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taeko: Configure GPIOs according to schematics
by Joey Peng (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Tim Wawrzynczak, YH Lin. Hello build bot (Jenkins), Tim Wawrzynczak, YH Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56754 to look at the new patch set (#2). Change subject: mb/google/brya/variants/taeko: Configure GPIOs according to schematics ...................................................................... mb/google/brya/variants/taeko: Configure GPIOs according to schematics Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 --- A src/mainboard/google/brya/variants/taeko/Makefile.inc A src/mainboard/google/brya/variants/taeko/gpio.c 2 files changed, 221 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/56754/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Gerrit-Change-Number: 56754 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Calculate and configure SF Mask 2
by Arthur Heymans (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56717 ) Change subject: soc/intel/common: Calculate and configure SF Mask 2 ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/56717/comment/7198aafd_b739ccc8 PS1, Line 540: mov %ebx, %eax /* restore data_ways in eax */ : xorl %edx, %edx : mov $IA32_CR_SF_QOS_MASK_2, %ecx : wrmsr This adds new behavior for CAR_HAS_SF_MASKS with both SF_MASK_2BITS_PER_WAY and !SF_MASK_2BITS_PER_WAY. Is that intended? -- To view, visit https://review.coreboot.org/c/coreboot/+/56717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Gerrit-Change-Number: 56717 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 02 Aug 2021 05:33:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taeko: Configure GPIOs according to schematics
by Joey Peng (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Joey Peng, Tim Wawrzynczak. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56754 ) Change subject: mb/google/brya/variants/taeko: Configure GPIOs according to schematics ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Gerrit-Change-Number: 56754 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Aug 2021 05:25:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taeko: Configure GPIOs according to schematics
by build bot (Jenkins) (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56754 ) Change subject: mb/google/brya/variants/taeko: Configure GPIOs according to schematics ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/taeko/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125520): https://review.coreboot.org/c/coreboot/+/56754/comment/4d3fd292_cf2dff5a PS1, Line 219: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/56754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Gerrit-Change-Number: 56754 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Aug 2021 05:23:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taeko: Configure GPIOs according to schematics
by Joey Peng (Code Review) 02 Aug '21

02 Aug '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56754 ) Change subject: mb/google/brya/variants/taeko: Configure GPIOs according to schematics ...................................................................... mb/google/brya/variants/taeko: Configure GPIOs according to schematics Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 --- A src/mainboard/google/brya/variants/taeko/Makefile.inc A src/mainboard/google/brya/variants/taeko/gpio.c 2 files changed, 221 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/56754/1 diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.inc b/src/mainboard/google/brya/variants/taeko/Makefile.inc new file mode 100644 index 0000000..8914639 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c new file mode 100644 index 0000000..9c495d4 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_override_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A9 : ESPI_CLK ==> ESPI_CLK */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A11, UP_20K, 1, DEEP), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_A17, UP_20K, 1, DEEP), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ + PAD_CFG_GPI_INT(GPP_A23, UP_20K NONE, PLTRST, EDGE_BOTH), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, UP_20K, 1, DEEP), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, UP_20K, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, UP_20K, 0, DEEP), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : SML1DATA ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), + + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, UP_20K, 1, DEEP), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_D4, UP_20K, 1, DEEP), + /* D5 : SRCCLKREQ0# ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + /* D17 : UART1_RXD ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, UP_20K, 1, DEEP), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> HPS_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, UP_20K, NONE, PLTRST, EDGE_BOTH), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E6 : THC0_SPI1_RST# ==> NC */ + PAD_NC(GPP_E6, NONE), + /* E7 : PROC_GP1 ==> EN_HPS_PWR */ + PAD_CFG_GPO(GPP_E7, UP_20K, 1, DEEP), + /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, UP_20K, 1, DEEP), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_F9, 0, PLTRST), + /* F15 : GSXSRESET# ==> FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F15, UP_20K NONE, DEEP, LEVEL, INVERT), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL ==> VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : BP105_CTRL ==> PP1050_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, UP_20K, 1, DEEP), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, UP_20K, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, UP_20K, 1, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, UP_20K, 1, DEEP), +}; + +const struct pad_config *__weak variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/56754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Gerrit-Change-Number: 56754 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen
by Ren Kuo (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Furquan Shaikh, Ren Kuo, Shou-Chieh Hsu, Karthik Ramasubramanian. Hello build bot (Jenkins), David Wu, Furquan Shaikh, Tyler Wang, Shou-Chieh Hsu, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56685 to look at the new patch set (#18). Change subject: mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen ...................................................................... mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen The all shipped magolor and maglia has been writed SSFC= 0x840. The value is defined as 5M MIPI Camera.But the value:0x840 will confilict with the updated touchcreen field. It will cause some touchsreen no funtion if make auto-update new firmware.The CL would correct the field error. The original fields: CAMERA_WFC 38 40 TS_SOURCE 41 44 Correct fields: MIPI Cam CAMERA_WFC 38 40 CAMERA_UFC 41 42 CAMERA_VCM 43 44 Touch-screen TS_SOURCE 45 48 The SSFC value of Magolor: CAMERA_OVTI5675 5M AF (SSFC = 0x840) CAMERA_OVTI8856 8M AF (SSFC = 0x880) BUG=b:194639170 TEST=Build firmware and verify on camera and touch-sreen devices Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/56685/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/56685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1 Gerrit-Change-Number: 56685 Gerrit-PatchSet: 18 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen
by Ren Kuo (Code Review) 02 Aug '21

02 Aug '21

Attention is currently required from: Furquan Shaikh, Ren Kuo, Shou-Chieh Hsu, Karthik Ramasubramanian. Hello build bot (Jenkins), David Wu, Furquan Shaikh, Tyler Wang, Shou-Chieh Hsu, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56685 to look at the new patch set (#17). Change subject: mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen ...................................................................... mb/google/dedede/var/magolor: modify SSFC for camera and touchscreen The all shipped magolor and maglia has been writed SSFC= 0x840. The value is defined as 5M MIPI Camera.But the value:0x840 will confilict with the updated touchcreen field. It will cause some touchsreen no funtion if make auto-update new firmware.The CL would correct the field error. The original fields: CAMERA_WFC 38 40 TS_SOURCE 41 44 Correct fields: MIPI Cam CAMERA_WFC 38 40 CAMERA_UFC 41 42 CAMERA_VCM 43 44 Touch-screen TS_SOURCE 45 48 The SSFC value of Magolor: CAMERA_OVTI5675 5M AF (SSFC = 0x840) CAMERA_OVTI8856 8M AF (SSFC = 0x880) BUG=b:189852808 TEST=Build firmware and verify on camera and touch-sreen devices Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/56685/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/56685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1 Gerrit-Change-Number: 56685 Gerrit-PatchSet: 17 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2021