Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56762 )
Change subject: mb/google/dedede: Create bugzzy variant
......................................................................
mb/google/dedede: Create bugzzy variant
Create the bugzzy variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192521391
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BUGZZY
Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com>
Change-Id: I851b9a75c387586d2fb84b762788e962f33472b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56762
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/Kconfig.name
A src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
A src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h
A src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc
A src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt
A src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt
A src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
8 files changed, 97 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
Raymond Chung: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 3cf1a3a..9437ddc 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -111,6 +111,7 @@
default "Haboki" if BOARD_GOOGLE_HABOKI
default "Cappy" if BOARD_GOOGLE_CAPPY
default "Cappy2" if BOARD_GOOGLE_CAPPY2
+ default "Bugzzy" if BOARD_GOOGLE_BUGZZY
config MAX_CPUS
int
@@ -148,6 +149,7 @@
default "haboki" if BOARD_GOOGLE_HABOKI
default "cappy" if BOARD_GOOGLE_CAPPY
default "cappy2" if BOARD_GOOGLE_CAPPY2
+ default "bugzzy" if BOARD_GOOGLE_BUGZZY
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index 6cdd4de..98a2298 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -159,3 +159,10 @@
bool "-> Cappy2"
select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
select BASEBOARD_DEDEDE_LAPTOP
+
+config BOARD_GOOGLE_BUGZZY
+ bool "-> Bugzzy"
+ select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
+ select BASEBOARD_DEDEDE_LAPTOP
+ select DRIVERS_GENERIC_MAX98357A
+ select DRIVERS_I2C_DA7219
diff --git a/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
new file mode 100644
index 0000000..08870e0
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h b/src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h
new file mode 100644
index 0000000..9078664
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc b/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc
new file mode 100644
index 0000000..b0ca222
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder.spd.hex
diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt
new file mode 100644
index 0000000..e4258b5
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
+# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
new file mode 100644
index 0000000..df3fb86
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -0,0 +1,55 @@
+chip soc/intel/jasperlake
+
+ # USB Port Configuration
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Trackpad |
+ #| I2C1 | Digitizer |
+ #| I2C2 | Touchscreen |
+ #| I2C3 | Camera |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 66,
+ .fall_time_ns = 90,
+ .data_hold_time_ns = 350,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ }
+ },
+ }"
+ device domain 0 on
+ device pci 14.0 on end
+ device pci 15.0 on end
+ device pci 15.2 on end
+ device pci 1c.7 on end
+ device pci 19.0 on end
+ device pci 1f.3 on end
+ end
+end
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I851b9a75c387586d2fb84b762788e962f33472b5
Gerrit-Change-Number: 56762
Gerrit-PatchSet: 3
Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com>
Gerrit-Reviewer: Edward Doan <edoan(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Henry Sun <henrysun(a)google.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com>
Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com>
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Gerrit-MessageType: merged
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56834 )
Change subject: drivers/uart/acpi: Update _S0W return value to D3hot
......................................................................
drivers/uart/acpi: Update _S0W return value to D3hot
In order to support wake from D3cold, most devices require extra
circuitry and possibly out-of-band communications to the host.
Therefore, assume that most UARTs that do have wake capabilities support
wake from D3hot rather than D3cold.
BUG=b:187228954
TEST=compile
Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/drivers/uart/acpi/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/56834/1
diff --git a/src/drivers/uart/acpi/acpi.c b/src/drivers/uart/acpi/acpi.c
index d4b14aa..3081182 100644
--- a/src/drivers/uart/acpi/acpi.c
+++ b/src/drivers/uart/acpi/acpi.c
@@ -89,7 +89,7 @@
/* Wake capabilities */
if (config->wake) {
- acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD);
+ acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
acpigen_write_PRW(config->wake, SLP_TYP_S3);
};
--
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Gerrit-Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400
Gerrit-Change-Number: 56834
Gerrit-PatchSet: 1
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Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56835 )
Change subject: soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4
......................................................................
soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4
The code is clearer when ACPI_DEVICE_SLEEP_D3_COLD is used instead of
the number 4.
Change-Id: I4b0ade1cd0b4b9cdb59f90f8d455269d0b69ed86
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/56835/1
diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
index 3d231b6..816df05 100644
--- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c
+++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
@@ -258,7 +258,7 @@
acpigen_write_device(acpi_device_name(dev));
acpigen_write_ADR(0);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
- acpigen_write_name_integer("_S0W", 4);
+ acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD);
dsd = acpi_dp_new_table("_DSD");
pkg = acpi_dp_new_table(PCIE_RTD3_STORAGE_UUID);
--
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Gerrit-Change-Number: 56835
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56833 )
Change subject: drivers/spi/acpi: Update _S0W return value to D3hot
......................................................................
drivers/spi/acpi: Update _S0W return value to D3hot
In order to support wake from D3cold, most devices require extra
circuitry and possibly out-of-band communications to the host.
Therefore, assume that most SPI peripherals that do have wake
capabilities support wake from D3hot rather than D3cold.
This also allows coreboot to expose a power resource to perform power
sequencing for a SPI peripheral that is intended to retain power in
S3/S0ix.
If support for a device with d3cold wake support is needed, it could be
added in later as an option.
BUG=b:187228954
TEST=compile
Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/drivers/spi/acpi/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/56833/1
diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c
index b23bc9d..abebd88 100644
--- a/src/drivers/spi/acpi/acpi.c
+++ b/src/drivers/spi/acpi/acpi.c
@@ -125,7 +125,7 @@
/* Wake capabilities */
if (config->wake) {
- acpigen_write_name_integer("_S0W", 4);
+ acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
acpigen_write_PRW(config->wake, 3);
};
--
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Gerrit-Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577
Gerrit-Change-Number: 56833
Gerrit-PatchSet: 1
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56832 )
Change subject: drivers/i2c/da7219: Update _S0W to D3hot
......................................................................
drivers/i2c/da7219: Update _S0W to D3hot
The DA7219 does not support wake from D3cold, therefore update the
return value of _S0W from D3cold to D3hot.
BUG=b:187228954
TEST=compile
Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/drivers/i2c/da7219/da7219.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56832/1
diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c
index 0423460..80c5272 100644
--- a/src/drivers/i2c/da7219/da7219.c
+++ b/src/drivers/i2c/da7219/da7219.c
@@ -36,7 +36,7 @@
acpigen_write_name_string("_HID", DA7219_ACPI_HID);
acpigen_write_name_integer("_UID", 1);
acpigen_write_name_string("_DDN", dev->chip_ops->name);
- acpigen_write_name_integer("_S0W", 4);
+ acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
acpigen_write_STA(acpi_device_status(dev));
/* Resources */
--
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Attention is currently required from: Jason Glenesk, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56450 )
Change subject: soc/amd/picasso: Move IVRS generation code to common
......................................................................
Patch Set 3: Code-Review+2
--
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