Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56855 )
Change subject: MAINTAINERS: add AMD Stoneyridge SoC
......................................................................
MAINTAINERS: add AMD Stoneyridge SoC
I don't have a stoneyridge platform, so I'll set it to Odd Fixes instead
of Maintained.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Idc4d98fd35d1b2f2d8165909c0fce141c6ca100d
---
M MAINTAINERS
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/56855/1
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c94ff8..590c5c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -621,6 +621,12 @@
F: src/soc/amd/picasso/
F: src/vendorcode/amd/fsp/picasso/
+AMD Stoneyridge
+M: Marshall Dawson <marshalldawson3rd(a)gmail.com>
+M: Felix Held <felix-coreboot(a)felixheld.de>
+S: Odd Fixes
+F: src/soc/amd/stoneyridge/
+
INTEL ALDERLAKE SOC
M: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
S: Maintained
--
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56854 )
Change subject: MAINTAINERS: add missing vendorcode/amd/fsp/cezanne directory
......................................................................
MAINTAINERS: add missing vendorcode/amd/fsp/cezanne directory
The Cezanne FSP headers are located in that directory, so add it to the
Cezanne SoC folders in the maintainers file.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I4f4894f0b01fa916492f57a730c62f29c5f7c796
---
M MAINTAINERS
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/56854/1
diff --git a/MAINTAINERS b/MAINTAINERS
index 5136822..1c94ff8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -602,6 +602,7 @@
M: Raul E Rangel <rrangel(a)chromium.org>
S: Maintained
F: src/soc/amd/cezanne/
+F: src/vendorcode/amd/fsp/cezanne/
AMD common SoC code
M: Marshall Dawson <marshalldawson3rd(a)gmail.com>
--
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56853 )
Change subject: mb/*/brya/adlrvp: move device cpu_cluster to soc/chipset.cb
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56853/comment/0ab662f8_3c37ebfe
PS1, Line 7: mb/*/brya/adlrvp
nit: mb/*/{adlrvp, brya}: Move cpu_cluster static configuration to chipset.cb
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Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56759 )
Change subject: mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> @Tim, are you suggesting to introduce chipset.cb into jsl, i don't see that in soc directory. […]
True Subrata...we didn't have chipset.cb design in JSL...it's available from TGL onwards.
I have done changes for ADL to move device cpu_cluster into chipset.cb here:
https://review.coreboot.org/c/coreboot/+/56853/1
If we agree, then I'll push patches for TGL too 😊
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Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56853 )
Change subject: mb/*/brya/adlrvp: move device cpu_cluster to soc/chipset.cb
......................................................................
mb/*/brya/adlrvp: move device cpu_cluster to soc/chipset.cb
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/soc/intel/alderlake/chipset.cb
5 files changed, 2 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56853/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 1627961..eb85cb5 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -1,7 +1,5 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_E"
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 3591a7b..8a779bc 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -1,7 +1,5 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
# GPE configuration
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index f4852b9..d4a2eb7 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -1,7 +1,5 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 3669c86..b28f387 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -6,8 +6,6 @@
end
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 532ec38..2d5c54e 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -1,5 +1,7 @@
chip soc/intel/alderlake
+ device cpu_cluster 0 on end
+
register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
--
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Change subject: mb/*/brya/adlrvp: Remove hardcoding of BSP APIC ID
......................................................................
mb/*/brya/adlrvp: Remove hardcoding of BSP APIC ID
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
4 files changed, 6 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/56852/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index b6dbf4d..1627961 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+
+ device cpu_cluster 0 on end
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index aa72ae1..3591a7b 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+
+ device cpu_cluster 0 on end
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 65dc9ca..f4852b9 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -1,8 +1,6 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
# GPE configuration
# Note that GPE events called out in ASL code rely on this
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index ac80caf..3669c86 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -6,9 +6,7 @@
end
chip soc/intel/alderlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
# GPE configuration
# Note that GPE events called out in ASL code rely on this
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Change subject: mb/google/guybrush: Enable STT in device tree
......................................................................
Patch Set 2: Code-Review+1
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Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56826 )
Change subject: mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56826/comment/0ddb28c2_c98a729f
PS2, Line 9: Keep the clock source for PCIe slots as always on. Also turn off the
> maybe specify that the clock sources for the PCIe slots are 3 and 4?
Done
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