Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56852 )
Change subject: mb/*/brya/adlrvp: Remove hardcoding of BSP APIC ID ......................................................................
mb/*/brya/adlrvp: Remove hardcoding of BSP APIC ID
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None BRANCH=None TEST=Check if there is no functional impact on the board.
Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8 Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb 4 files changed, 6 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/56852/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index b6dbf4d..1627961 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -1,7 +1,6 @@ chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + + device cpu_cluster 0 on end
# GPE configuration register "pmc_gpe0_dw0" = "GPP_A" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index aa72ae1..3591a7b 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -1,7 +1,6 @@ chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + + device cpu_cluster 0 on end
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 65dc9ca..f4852b9 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/alderlake
- device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ac80caf..3669c86 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -6,9 +6,7 @@ end chip soc/intel/alderlake
- device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end
# GPE configuration # Note that GPE events called out in ASL code rely on this
-
Maulik V Vaghela (Code Review)