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Hello build bot (Jenkins), ritul guru, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot
......................................................................
mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot
Keep the clock source for PCIe slots as always on. Also turn off the
unused (0/1/5/6) clock sources. Currently bilby only uses clock sources
2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe
external slot. And clock source 2 is routed for M.2 PCIe slot.
TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot.
Signed-off-by: Aamir Bohra <aamirbohra(a)gmail.com>
Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f
---
M src/mainboard/amd/bilby/devicetree.cb
1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/56826/3
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Gerrit-Change-Number: 56826
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Change subject: mb/google/brya: create dynamic power limits mechanism for thermal
......................................................................
mb/google/brya: create dynamic power limits mechanism for thermal
Add dynamic power limits selection mechanism for brya board based on
CPU SKUs which is detectable at runtime.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya with below messages,
On brya (282):
Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000)
On brya (482):
Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000)
Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/brya/mainboard.c
M src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc
A src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
4 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/56515/8
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/variants/brya0: set power limits for thermal
......................................................................
mb/google/brya/variants/brya0: set power limits for thermal
Set power limits for brya0 variant board based on CPU SKUs
which is detectable at runtime.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 variant board with below messages,
On brya (282):
Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000)
On brya (482):
Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000)
Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/brya/variants/brya0/Makefile.inc
A src/mainboard/google/brya/variants/brya0/ramstage.c
2 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56622/5
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18970 )
Change subject: util/lint: Show an error if a symbol is created in two choice blocks
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> ack.
Is that "ack, we should change that" or "ack, that was/is intended"? ;-)
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56828 )
Change subject: mb/google/dedede/var/storo: Fixed iasl can not run on Dut
......................................................................
Patch Set 1: Code-Review+2
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