coreboot-gerrit August 2021

coreboot-gerrit@coreboot.org

1 participants
4519 discussions

Change in coreboot[master]: mb/google/dedede/var/cret: Fix DPTF passive and critical policies
by Sumeet R Pawnikar (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Dtrain Hsu, Henry Sun, Shou-Chieh Hsu, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56870 ) Change subject: mb/google/dedede/var/cret: Fix DPTF passive and critical policies ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I849662cbb3adc8e528d65af2c90e7c8e4880d607 Gerrit-Change-Number: 56870 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 11:45:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/variants/primus: Remove DPTF fan control
by Sumeet R Pawnikar (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Tim Wawrzynczak, Scott Chao. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56879 ) Change subject: mb/google/brya/variants/primus: Remove DPTF fan control ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If758d75ff24c88c9eaf0de90ac0ef08d172a2edd Gerrit-Change-Number: 56879 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 11:44:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush: Enable STT in device tree
by Paul Menzel (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Diana Zigterman, Jason Glenesk, Nikolai Vyssotski. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55434 ) Change subject: mb/google/guybrush: Enable STT in device tree ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55434/comment/2ccb5268_b0c26c54 PS3, Line 66: register "stt_skin_temp_apu" = "0x2D00" It’d be great if the unit would be part of the name, and, if degree celcius, it’d be to the basis ten. -- To view, visit https://review.coreboot.org/c/coreboot/+/55434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Gerrit-Change-Number: 55434 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Diana Zigterman <dzigterman(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Diana Zigterman <dzigterman(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 11:27:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation/util/kconfig: Remove silentoldconfig
by Paul Menzel (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56878 ) Change subject: Documentation/util/kconfig: Remove silentoldconfig ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0 Gerrit-Change-Number: 56878 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 11:26:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: Add support for DDR5 MR SKU
by Meera Ravindranath (Code Review) 09 Aug '21

09 Aug '21

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56881 ) Change subject: mb/intel/adlrvp: Add support for DDR5 MR SKU ...................................................................... mb/intel/adlrvp: Add support for DDR5 MR SKU DDR5 Maple ridge SKU uses a Memory down DIMM configuration. This CL adds support for the same. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882 --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex 3 files changed, 41 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/56881/1 diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index cccd258..df08e50 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -35,6 +35,11 @@ .cbfs_index = get_spd_index(), }; + const struct mem_spd mr_ddr5_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), + }; + const struct mem_spd ddr4_ddr5_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, .smbus = { @@ -53,9 +58,11 @@ case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - case ADL_P_DDR5_2: memcfg_init(m_cfg, mem_config, &ddr4_ddr5_spd_info, half_populated); break; + case ADL_P_DDR5_2: + memcfg_init(m_cfg, mem_config, &mr_ddr5_spd_info, half_populated); + break; case ADL_P_LP4_1: case ADL_P_LP4_2: case ADL_P_LP5_1: diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 5c5c1b4..4ab055d 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -6,5 +6,5 @@ SPD_SOURCES += adlrvp_lp5 # 0b003 SPD_SOURCES += empty # 0b004 SPD_SOURCES += empty # 0b005 -SPD_SOURCES += empty # 0b006 +SPD_SOURCES += adlrvp_ddr5_mr # 0b006 SPD_SOURCES += adlrvp_lp5 # 0b007 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex new file mode 100644 index 0000000..80ef521 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex @@ -0,0 +1,32 @@ +30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00 +00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41 +1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00 +00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/56881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882 Gerrit-Change-Number: 56881 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/intel/adlrvp: create dynamic power limits mechanism for thermal
by Sumeet R Pawnikar (Code Review) 09 Aug '21

09 Aug '21

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56880 ) Change subject: mb/intel/adlrvp: create dynamic power limits mechanism for thermal ...................................................................... mb/intel/adlrvp: create dynamic power limits mechanism for thermal Add dynamic power limits selection mechanism for aldrvp board. BUG=None BRANCH=None TEST=Build FW and test on adlrvp with DPTF tool On adlrvp (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (55000, 55000) On adlrvp (682): Overriding DPTF power limits PL1 (5000, 45000) PL2 (115000, 115000) Change-Id: Id1aef0125c6e1e105665172f19bda271e232d94f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/intel/adlrvp/Makefile.inc M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/ramstage.c 4 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56880/1 diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index ca9ba14..04c1645 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -24,6 +24,7 @@ ramstage-y += mainboard.c ramstage-y += board_id.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += ramstage.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9a94db2..bc2a57e 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -35,4 +35,17 @@ size_t variant_memory_sku(void); const struct mb_cfg *variant_memory_params(void); + +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); +struct cpu_power_limits { + uint16_t mchid; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; +}; +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index 1e1e318..ce3dc6f 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -28,6 +28,13 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); + + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ } #if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c new file mode 100644 index 0000000..25a7c5b --- /dev/null +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#include <drivers/intel/dptf/chip.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ + /* PL2 values are for performance configuration */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 55000, 55000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 64000, 64000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 115000, 115000 }, +}; + +void variant_update_power_limits(void) +{ + const struct device_path policy_path[] = { + { .type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_DPTF}, + { .type = DEVICE_PATH_GENERIC, .generic.id = 0} + }; + + const struct device *policy_dev = find_dev_nested_path(pci_root_bus(), + policy_path, ARRAY_SIZE(policy_path)); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { + if (mchid == limits[i].mchid) { + struct dptf_power_limits *settings = &config->controls.power_limits; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + printk(BIOS_INFO, "sumeet: Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power); + } + } +} + +void variant_devtree_update(void) +{ + variant_update_power_limits(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1aef0125c6e1e105665172f19bda271e232d94f Gerrit-Change-Number: 56880 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/intel/adlrvp: create dynamic power limits mechanism for thermal
by Sumeet R Pawnikar (Code Review) 09 Aug '21

09 Aug '21

Sumeet R Pawnikar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56516 ) Change subject: mb/intel/adlrvp: create dynamic power limits mechanism for thermal ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/56516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30a1e3aca2d27c64ee427ff7864639483448aa94 Gerrit-Change-Number: 56516 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: mb/google/guybrush: Enable STT in device tree
by Jason Glenesk (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Diana Zigterman, Paul Menzel, Nikolai Vyssotski. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55434 ) Change subject: mb/google/guybrush: Enable STT in device tree ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55434/comment/967d6584_a25d9497 PS2, Line 9: STT > Please use the long name in the commit message body. done -- To view, visit https://review.coreboot.org/c/coreboot/+/55434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Gerrit-Change-Number: 55434 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Diana Zigterman <dzigterman(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Diana Zigterman <dzigterman(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 09:07:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush: Enable STT in device tree
by Jason Glenesk (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Diana Zigterman, Jason Glenesk, Nikolai Vyssotski. Hello build bot (Jenkins), Marshall Dawson, Diana Zigterman, Nikolai Vyssotski, Rob Barnes, Matt Papageorge, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55434 to look at the new patch set (#3). Change subject: mb/google/guybrush: Enable STT in device tree ...................................................................... mb/google/guybrush: Enable STT in device tree Enable Skin Temperature Tracking with initial configuration settings. BUG=b:190732595 TEST=Confirm that AGT tool can successfully complete data collection Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/55434/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Gerrit-Change-Number: 55434 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Diana Zigterman <dzigterman(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Diana Zigterman <dzigterman(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/inteltool: Add support for GLK
by Michał Żygowski (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Sean Rhodes, Igor Bagnucki, Stefan Reinauer, Name of user not set #1003165, Piotr Król. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51130 ) Change subject: util/inteltool: Add support for GLK ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Without a case in gpio.c, it just ends up at the default "is not (yet)" supported. […] It might be wise to look at CB:36033 as it is more complete than this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/51130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017789c9e23e355214deced29efcb3532c449981 Gerrit-Change-Number: 51130 Gerrit-PatchSet: 3 Gerrit-Owner: Name of user not set #1003165 Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Name of user not set #1003165 Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 08:48:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2021