Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56878 )
Change subject: Documentation/util/kconfig: Remove silentoldconfig
......................................................................
Documentation/util/kconfig: Remove silentoldconfig
The "silentoldconfig" target has been removed in Linux 5.13's kconfig
(CB:37152). As explained by Michal Marek at
https://lkml.org/lkml/2011/8/31/189, the "silentoldconfig" target has
become an internal interface and "oldconfig" is just as silent now.
Therefore, correct the target for syntax checking.
Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M Documentation/getting_started/kconfig.md
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/56878/1
diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md
index 819eb72..fff186e 100644
--- a/Documentation/getting_started/kconfig.md
+++ b/Documentation/getting_started/kconfig.md
@@ -1188,7 +1188,7 @@
## Syntax Checking:
The Kconfig utility does some basic syntax checking on the Kconfig tree.
-Running "make silentoldconfig" will show any errors that the Kconfig utility
+Running "make oldconfig" will show any errors that the Kconfig utility
sees.
### util/kconfig_lint
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Change subject: drivers/generic/alc1015: Add HID to support alc1019
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Should the directory be renamed to alc101x?
wait for the kernel review, will change if needed.
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: drivers/generic/alc1015: Add HID to support alc1019
......................................................................
drivers/generic/alc1015: Add HID to support alc1019
ALC1019 will use the ACPI compatible and share the same driver with
ALC1015. Add HID to support more compatible ICs.
BUG=b:195891240
TEST=: ALC1019P driver can probe properly.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5
---
M src/drivers/generic/alc1015/alc1015.c
M src/drivers/generic/alc1015/chip.h
2 files changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/56877/2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56877 )
Change subject: drivers/generic/alc1015: Add HID to support alc1019
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Should the directory be renamed to alc101x?
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Change subject: drivers/generic/alc1015: Add HID to support alc1019
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56877/comment/ee321fa1_6ae9c5ec
PS1, Line 9: campitable
compatible
https://review.coreboot.org/c/coreboot/+/56877/comment/7ab9f35f_2248aa0d
PS1, Line 10: campitable
Ditto.
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Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 )
Change subject: [RFC,WIP] ChromeOS: Create pseudo-device ACPI NVS
......................................................................
Patch Set 7: Code-Review+1
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Change subject: drivers/generic/alc1015: Add HID to support alc1019
......................................................................
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PS1:
prepare for brya new DB.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56759 )
Change subject: mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID
......................................................................
mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik(a)intel.com>
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Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
2 files changed, 2 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index cb5321c..38b1da27 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -27,9 +27,7 @@
end
chip soc/intel/jasperlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
# GPE configuration
# Note that GPE events called out in ASL code rely on this
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 34f9eae..262e27df 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -1,8 +1,6 @@
chip soc/intel/jasperlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
# GPE configuration
# Note that GPE events called out in ASL code rely on this
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56758 )
Change subject: soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus
......................................................................
soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus
coreboot always assumes that BSP APIC ID will always be 0 but as
per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can
be any processor whose index/APIC ID might not be 0.
To handle this situation, init_cpu call is required to modify to
handle dynamic detection of APIC ID from BSP instead of hardcoding
always through devicetree. Function has been updated to create
a new node with actual BSP APIC ID when devicetree doesn't contain
APIC ID defined. In case APID ID is defined, function will use a
node with the APIC ID defined in devicetree.
Changes also requires to remove "lapic 0" hardcoding from devicetree
to allow code to fill BSP APIC ID dynamically. Otherwise coreboot
will create an extra node for CPU with APIC ID 0 and it'll show as a
extra node in kernel. This will cause kernel to report wrong (extra)
core count information then actually present.
BUG=None
BRANCH=None
TEST=Boot the JSL system and observe there is no functional impacts.
Without this CL kernel core count in `lscpu` = 3
With this CL, kernel core count is corrected to 2.
Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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Reviewed-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 13 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index c31a6f7..bf47b2e 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -115,14 +115,25 @@
* this call if user has selected USE_INTEL_FSP_MP_INIT).
* 2. coreboot would like to take APs control back after FSP-S has done with MP
* initialization based on user select USE_INTEL_FSP_MP_INIT.
+ *
+ * This function would use cpu_cluster as a device and APIC device as a linked list to
+ * the cpu cluster. This function adds a node in case the mainboard doesn't have a lapic id
+ * hardcoded in devicetree, and then fills with the actual BSP APIC ID.
+ * This allows coreboot to dynamically detect the LAPIC ID of BSP.
+ * In case the mainboard has an APIC ID defined in devicetree, a link will be present and
+ * creation of the new node will be skipped. This node will have the APIC ID defined
+ * in devicetree.
*/
void init_cpus(void)
{
struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
assert(dev != NULL);
- if (dev && dev->link_list)
- soc_init_cpus(dev->link_list);
+ /* In case link to APIC device is not found, create the one */
+ if (!dev->link_list)
+ add_more_links(dev, 1);
+
+ soc_init_cpus(dev->link_list);
}
static void coreboot_init_cpus(void *unused)
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