coreboot-gerrit August 2021

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Change in coreboot[master]: vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count
by Hung-Te Lin (Code Review) 08 Aug '21

08 Aug '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56849 ) Change subject: vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count ...................................................................... vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM frequency counts to reduce DRAM initialization time by about 100ms. BUG=b:195274787 Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index b5de592..b5b9ae1 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -1882,6 +1882,9 @@ ett_fix_freq = 1; /* only 1600 & 4266 */ #endif + if (CONFIG(MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT)) + ett_fix_freq = 0x1; // 4266, 1600 + if (ett_fix_freq != 0xff) gAndroid_DVFS_en = FALSE; -- To view, visit https://review.coreboot.org/c/coreboot/+/56849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2 Gerrit-Change-Number: 56849 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/libpayload: add MTK_TIMER_V2 config
by Hung-Te Lin (Code Review) 08 Aug '21

08 Aug '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56845 ) Change subject: payloads/libpayload: add MTK_TIMER_V2 config ...................................................................... payloads/libpayload: add MTK_TIMER_V2 config The timer structure (in particular, the offset to memory addresses) on recent MTK SoCs for example MT8195 has been changed. BUG=b:195274787 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac Reviewed-on: https://review.coreboot.org/c/coreboot/+/56845 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/drivers/timer/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 175e4bb..406457a 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -45,6 +45,9 @@ config TIMER_MTK bool "Timer for MediaTek" +config TIMER_MTK_V2 + bool "Timer for MediaTek V2" + endchoice config TIMER_GENERIC_HZ @@ -53,6 +56,7 @@ default 6250000 if TIMER_IPQ806X default 24000000 if TIMER_MCT default 13000000 if TIMER_MTK + default 13000000 if TIMER_MTK_V2 default 24000000 if TIMER_RK3288 default 24000000 if TIMER_RK3399 default 1000000 if TIMER_TEGRA_1US @@ -67,6 +71,7 @@ default 0x0200A028 if TIMER_IPQ806X default 0x101C0100 if TIMER_MCT default 0x10008068 if TIMER_MTK + default 0x100080A8 if TIMER_MTK_V2 default 0xff810028 if TIMER_RK3288 default 0xff850008 if TIMER_RK3399 default 0x60005010 if TIMER_TEGRA_1US @@ -79,6 +84,7 @@ default 0x004A2004 if TIMER_IPQ40XX default 0x101C0104 if TIMER_MCT default 0x10008078 if TIMER_MTK + default 0x100080B0 if TIMER_MTK_V2 default 0xff81002C if TIMER_RK3288 default 0xff85000C if TIMER_RK3399 default 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/56845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac Gerrit-Change-Number: 56845 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: Improve boot time by raising little CPU frequency
by Hung-Te Lin (Code Review) 08 Aug '21

08 Aug '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56844 ) Change subject: mb/google/cherry: Improve boot time by raising little CPU frequency ...................................................................... mb/google/cherry: Improve boot time by raising little CPU frequency Raise little CPU to 2GHz at romstage to improve boot time by about 100 ms. BUG=b:195274787 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Id6aac8f9db86a6c1e61ea94863f2cbde12c0482e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56844 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/romstage.c 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index c11fef4..71291c2 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -1,21 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <delay.h> #include <soc/clkbuf.h> #include <soc/emi.h> #include <soc/i2c.h> #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/mt6360.h> +#include <soc/pll_common.h> #include <soc/pmif.h> #include <soc/rtc.h> #include <soc/scp.h> +static void raise_little_cpu_freq(void) +{ + mt6359p_buck_set_voltage(MT6359P_SRAM_PROC1, 1000 * 1000); + mt6359p_buck_set_voltage(MT6359P_CORE, 1000 * 1000); + udelay(200); + mt_pll_raise_little_cpu_freq(2000 * MHz); + mt_pll_raise_cci_freq(1385 * MHz); +} + void platform_romstage_main(void) { mtk_pmif_init(); mt6359p_init(); mt6315_init(); + raise_little_cpu_freq(); mtk_i2c_bus_init(I2C7); if (CONFIG(BOARD_GOOGLE_CHERRY)) mt6360_init(I2C7); -- To view, visit https://review.coreboot.org/c/coreboot/+/56844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6aac8f9db86a6c1e61ea94863f2cbde12c0482e Gerrit-Change-Number: 56844 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/common: add mt6359p vcore support
by Hung-Te Lin (Code Review) 08 Aug '21

08 Aug '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56843 ) Change subject: soc/mediatek/common: add mt6359p vcore support ...................................................................... soc/mediatek/common: add mt6359p vcore support Add mt6359p vcore set/get support. To adjust frequency of little core, we need to adjust voltage of vcore. Signed-off-by: James Lo <james.lo(a)mediatek.corp-partner.google.com> Change-Id: Ibf49390ba78870b834c6d0b64e3f0f30f3494f18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56843 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/mt6359p.h M src/soc/mediatek/common/mt6359p.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/mt6359p.h b/src/soc/mediatek/common/include/soc/mt6359p.h index 996d2e8..5afac9f 100644 --- a/src/soc/mediatek/common/include/soc/mt6359p.h +++ b/src/soc/mediatek/common/include/soc/mt6359p.h @@ -18,6 +18,8 @@ PMIC_OTP_CON12 = 0x03a2, PMIC_OTP_CON13 = 0x03a4, PMIC_PWRHOLD = 0x0a08, + PMIC_VCORE_DBG0 = 0x1526, + PMIC_VCORE_ELR0 = 0x152c, PMIC_VGPU11_DBG0 = 0x15a6, PMIC_VGPU11_ELR0 = 0x15b4, PMIC_VS2_VOTER = 0x18aa, @@ -50,6 +52,7 @@ MT6359P_GPU11 = 0, MT6359P_SRAM_PROC1, MT6359P_SRAM_PROC2, + MT6359P_CORE, MT6359P_MAX, }; diff --git a/src/soc/mediatek/common/mt6359p.c b/src/soc/mediatek/common/mt6359p.c index 8ebcfc6..5a87c0d 100644 --- a/src/soc/mediatek/common/mt6359p.c +++ b/src/soc/mediatek/common/mt6359p.c @@ -177,6 +177,10 @@ vol_offset = 500000; vol_reg = PMIC_VSRAM_PROC2_ELR; break; + case MT6359P_CORE: + vol_offset = 506250; + vol_reg = PMIC_VCORE_ELR0; + break; default: die("ERROR: Unknown buck_id %u", buck_id); return; @@ -209,6 +213,11 @@ vol_offset = 500000; vol_reg = PMIC_VSRAM_PROC2_VOSEL1; break; + case MT6359P_CORE: + vol_shift = 0; + vol_offset = 506250; + vol_reg = PMIC_VCORE_DBG0; + break; default: die("ERROR: Unknown buck_id %u", buck_id); return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/56843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf49390ba78870b834c6d0b64e3f0f30f3494f18 Gerrit-Change-Number: 56843 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: early-init eMMC
by Hung-Te Lin (Code Review) 08 Aug '21

08 Aug '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56842 ) Change subject: mb/google/cherry: early-init eMMC ...................................................................... mb/google/cherry: early-init eMMC Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, Depthcharge needs it 20ms after started) so we have to start initialization in coreboot. BUG=b:195274787 TEST=emerge-cherry coreboot BRANCH=cherry Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: Idc86f9121fa4a34f09a683f7a81087c13ea3dd42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56842 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/mainboard.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 6b29f44..bb6dbac 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -14,6 +14,7 @@ #include <soc/dptx.h> #include <soc/gpio.h> #include <soc/i2c.h> +#include <soc/msdc.h> #include <soc/mt6360.h> #include <soc/mtcmos.h> #include <soc/regulator.h> @@ -39,6 +40,9 @@ DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8) DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12) +#define MSDC0_BASE 0x11230000 +#define MSDC0_TOP_BASE 0x11f50000 + #define MSDC0_DRV_VALUE 0x1b6db6db #define MSDC1_DRV_VALUE 0x1b6db #define MSDC1_GPIO_MODE0_VALUE 0x1 @@ -85,6 +89,8 @@ /* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */ SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); + + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); } static void configure_sdcard(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/56842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc86f9121fa4a34f09a683f7a81087c13ea3dd42 Gerrit-Change-Number: 56842 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: select mmc storage config
by Hung-Te Lin (Code Review) 08 Aug '21

08 Aug '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56841 ) Change subject: mb/google/cherry: select mmc storage config ...................................................................... mb/google/cherry: select mmc storage config Select mmc storage config for cherry. BUG=b:195274787 TEST=emerge-cherry coreboot BRANCH=cherry Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I67c8795b6e6fc121e8fe61c40da05593faa02d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56841 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/Kconfig M src/soc/mediatek/mt8195/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 6ded021..07a5781 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -27,6 +27,8 @@ select MAINBOARD_HAS_TPM2 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC config MAINBOARD_DIR default "google/cherry" diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 5cac723..26e0da9d 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -64,6 +64,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += mt6360.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c ramstage-y += ../common/pll.c pll.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/56841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67c8795b6e6fc121e8fe61c40da05593faa02d94 Gerrit-Change-Number: 56841 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create driblee variant
by Frank Wu (Code Review) 08 Aug '21

08 Aug '21

Attention is currently required from: Henry Sun, Paul Menzel, Aseda Aboagye, Karthik Ramasubramanian. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56798 ) Change subject: mb/google/dedede: Create driblee variant ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Hi Google, Would you help to review the CL? Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/56798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Gerrit-Change-Number: 56798 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 01:50:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Create corori variant
by Frank Wu (Code Review) 08 Aug '21

08 Aug '21

Attention is currently required from: Ian Feng, Henry Sun, Paul Menzel, Aseda Aboagye, Karthik Ramasubramanian. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56796 ) Change subject: mb/google/dedede: Create corori variant ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Hi Google, Would you help to review the CL? Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/56796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Gerrit-Change-Number: 56796 Gerrit-PatchSet: 6 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 01:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variant/taeko: Update devicetree settings
by Joey Peng (Code Review) 08 Aug '21

08 Aug '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, YH Lin. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56802 ) Change subject: mb/google/brya/variant/taeko: Update devicetree settings ...................................................................... Patch Set 6: (3 comments) File src/mainboard/google/brya/variants/taeko/overridetree.cb: https://review.coreboot.org/c/coreboot/+/56802/comment/6b868fe7_ba41e629 PS5, Line 67: probe AUDIO RT1011_ALC5682I_I2S > a `probe` statement can only be added when you have the `fw_config` section filled out already, for […] OK, we will remove probe since we only uses one audio codec. https://review.coreboot.org/c/coreboot/+/56802/comment/e7fe0e61_91647491 PS5, Line 75: probe AUDIO RT1011_ALC5682I_I2S > same Done https://review.coreboot.org/c/coreboot/+/56802/comment/f9a5ce16_0a28ad2e PS5, Line 83: probe AUDIO RT1011_ALC5682I_I2S > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Gerrit-Change-Number: 56802 Gerrit-PatchSet: 6 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Aug 2021 01:03:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variant/taeko: Update devicetree settings
by Joey Peng (Code Review) 08 Aug '21

08 Aug '21

Attention is currently required from: Joey Peng, Nick Vaccaro, YH Lin. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, YH Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56802 to look at the new patch set (#6). Change subject: mb/google/brya/variant/taeko: Update devicetree settings ...................................................................... mb/google/brya/variant/taeko: Update devicetree settings Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 255 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/56802/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Gerrit-Change-Number: 56802 Gerrit-PatchSet: 6 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2021