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Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56853
to look at the new patch set (#2).
Change subject: mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb
......................................................................
mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/soc/intel/alderlake/chipset.cb
5 files changed, 2 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56853/2
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56645 )
Change subject: mb/google/guybrush: Switch from 33MHz to 66MHz SPI Speed
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/56645/comment/5d04a145_9645bcf8
PS3, Line 13: 33M
> Makes sense. Thanks Felix! I think most parts support upto 50MHz for normal speed. […]
The way I remember it from older FCH, MMIO access right below 4 GiB will use either .normal_speed or .fast_speed while everything through the SPI driver layer will use .altio_speed.
In spi_ctrlr_xfer() register SPI_CMD_CODE 0x45 aliases/shadows 0x0 named SpiOpCode:
SpiOpCode. Read-write. Reset: 0. Specifies the SPI opcode in alternate program method.
We can find some old 3V parts marketed as dual-IO and 80MHz, which might fail with 66MHz as .fast_speed or .altio_speed. One example -- SST25VF064C, EOL 2015. If some of this change is pushed to older agesa/hudson better keep the default to 33MHz on all boards.
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Prasad Malisetty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53903 )
Change subject: libpayload: Add MMIO support in PCI lib
......................................................................
Patch Set 30:
(6 comments)
Patchset:
PS30:
Hi Furquan/ Arthur,
Thanks for the review.
I have modified the patch-set as per the latest comments. validation is in progress.
Hi Furquan, I have some questions on few of the comments. Could you please help me to confirm, so that I will update the changes and submit in next version patch set.
Thanks
-Prasad
File payloads/libpayload/drivers/pci_ops.c:
https://review.coreboot.org/c/coreboot/+/53903/comment/ff631722_7dc4b874
PS30, Line 31: ui
> use static?
Hi Arthur,
Sure, we will update in next version.
Thanks
-Prasad
https://review.coreboot.org/c/coreboot/+/53903/comment/e45e8cbb_1eaeadf8
PS30, Line 33: /* Get PCI MMCONFIG BASE address */
: uintptr_t get_pci_mmio_cfgbase(pcidev_t dev)
: {
: uintptr_t mmconf_base = (uintptr_t)lib_sysinfo.pci_mmio_cfg_base;
: u32 devfn = ((dev >> 3) & 0x1f) | (dev & 0x07);
:
: return (mmconf_base | devfn);
: }
:
: u8 pci_read_config8(pcidev_t dev, u16 reg)
: {
: void *addr;
: uintptr_t mmio_base = get_pci_mmio_cfgbase(dev);
:
: addr = (void *)(mmio_base | reg);
: return read8(addr);
: }
> Did you have a look at include/device/pci_mmio_cfg. […]
Yes, true. I will reuse and update the changes in next patch set version.
Thanks
-Prasad
File payloads/libpayload/include/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/53903/comment/faa37ac2_193ec49e
PS30, Line 247: void *mmio_config_base;
> You also want to expose the mmcfg size or number of busses (CONFIG_MMCONF_BUS_NUMBER)
I will check internally and update exact BUS number.
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/53903/comment/a253f792_04fa211e
PS30, Line 95: void lb_add_pci(struct lb_header *header)
> why not static? where else is this called?
Yes static only. no where else called. Will update the change in next patch set.
https://review.coreboot.org/c/coreboot/+/53903/comment/fc553f81_30d5db33
PS30, Line 499: lb_add_pci(head);
> guard with if (CONFIG(MMCONF_SUPPORT))
Sure, I will incorporate changes in next patch set.
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Edward Dai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56828 )
Change subject: mb/google/dedede/var/storo: Fixed iasl can not run on Dut
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi Reviewers, Please help to CQ+2 the CLs.
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Change subject: soc/mediatek/mt8192: initialize DFD
......................................................................
Patch Set 4:
(2 comments)
File src/soc/mediatek/mt8192/Kconfig:
https://review.coreboot.org/c/coreboot/+/56797/comment/f8b2db99_bf78ecb1
PS4, Line 70: This option enables DFD (Design for Debug) settings.
> Please extend the description in a followup.
maybe add some description like commit message in future version .
File src/soc/mediatek/mt8192/dfd.c:
https://review.coreboot.org/c/coreboot/+/56797/comment/599d0083_32741f2a
PS4, Line 9: printk(BIOS_INFO, "[%s]\n", __func__);
> This reads like a debug message.
maybe add more message like "dfd initialize" in future version.
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Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56850 )
Change subject: vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/O
......................................................................
vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/O
Disable reading of vdram/vddq/vmddr to reduce access of I2C
to reduce DRAM init time by about 30ms.
The values were only needed by HQA report and not needed on
production units.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56850
Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Yu-Ping Wu: Looks good to me, approved
Rex-BC Chen: Looks good to me, but someone else must approve
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index b5b9ae1..f39023b 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -273,10 +273,12 @@
#ifndef DDR_INIT_TIME_PROFILING
print("Read voltage for %d, %d\n", p->frequency, vGet_Current_SRAMIdx(p));
print("Vcore = %d\n", dramc_get_vcore_voltage());
+#ifdef FOR_HQA_REPORT_USED
print("Vdram = %d\n", dramc_get_vmdd_voltage(p->dram_type));
print("Vddq = %d\n", dramc_get_vmddq_voltage(p->dram_type));
print("Vmddr = %d\n", dramc_get_vmddr_voltage());
#endif
+#endif
#endif
#endif
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