coreboot-gerrit August 2021

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Change in coreboot[master]: mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codec
by Paul Fagerburg (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Sunwei Li, Henry Sun. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56795 ) Change subject: mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codec ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9121e75eaf46b43e6dc5ef2e31029a153c7a807d Gerrit-Change-Number: 56795 Gerrit-PatchSet: 8 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 15:28:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taeko: Configure GPIOs according to schematics
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56754 ) Change subject: mb/google/brya/variants/taeko: Configure GPIOs according to schematics ...................................................................... mb/google/brya/variants/taeko: Configure GPIOs according to schematics Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56754 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/mainboard/google/brya/variants/taeko/Makefile.inc A src/mainboard/google/brya/variants/taeko/gpio.c 2 files changed, 184 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.inc b/src/mainboard/google/brya/variants/taeko/Makefile.inc new file mode 100644 index 0000000..9fb63f5 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c new file mode 100644 index 0000000..a06659d --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D5 : SRCCLKREQ0# ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + /* D17 : UART1_RXD ==> NC */ + PAD_NC(GPP_D17, NONE), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL ==> VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : BP105_CTRL ==> PP1050_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +const struct pad_config *__weak variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Gerrit-Change-Number: 56754 Gerrit-PatchSet: 15 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: create dynamic power limits mechanism for thermal
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56880 ) Change subject: mb/intel/adlrvp: create dynamic power limits mechanism for thermal ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1aef0125c6e1e105665172f19bda271e232d94f Gerrit-Change-Number: 56880 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 09 Aug 2021 15:18:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Attention is currently required from: Tim Crawford, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56867 ) Change subject: soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56867/comment/4f7aa4d2_9e596940 PS2, Line 682: Probably would be good to explicitly set `SkipSsidProgramming` to 0 here as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/56867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e Gerrit-Change-Number: 56867 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 09 Aug 2021 15:15:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/brya0: set power limits for thermal
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56622 ) Change subject: mb/google/brya/variants/brya0: set power limits for thermal ...................................................................... mb/google/brya/variants/brya0: set power limits for thermal Set power limits for brya0 variant board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 variant board with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56622 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/brya0/Makefile.inc A src/mainboard/google/brya/variants/brya0/ramstage.c 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/Makefile.inc b/src/mainboard/google/brya/variants/brya0/Makefile.inc index cd8eb69..646fd09 100644 --- a/src/mainboard/google/brya/variants/brya0/Makefile.inc +++ b/src/mainboard/google/brya/variants/brya0/Makefile.inc @@ -2,3 +2,4 @@ ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/brya0/ramstage.c b/src/mainboard/google/brya/variants/brya0/ramstage.c new file mode 100644 index 0000000..0da8eb1 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ + /* PL2 values are for baseline config as per bug:191906315 comment #10 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6 Gerrit-Change-Number: 56622 Gerrit-PatchSet: 9 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: gimble: enable elan touchscreen
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56801 ) Change subject: gimble: enable elan touchscreen ...................................................................... gimble: enable elan touchscreen Enable Elan touchscreen and remove Goodix touchscreen. We also get confirmation by Elan that address is 0x15. BUG=b:195494292 BRANCH=none TEST=build coreboot and dmesg | grep hid, it showed i2c-ELAN9050:00. Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I20a7fd0b370803c14990b77bab302727af197ccb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56801 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 101e472..49626aa 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -125,23 +125,23 @@ end #I2C0 device ref i2c1 on chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "12" + register "generic.enable_delay_ms" = "6" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 0x5d on end + device i2c 0x15 on end end end device ref i2c5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/56801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20a7fd0b370803c14990b77bab302727af197ccb Gerrit-Change-Number: 56801 Gerrit-PatchSet: 4 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56835 ) Change subject: soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4 ...................................................................... soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4 The code is clearer when ACPI_DEVICE_SLEEP_D3_COLD is used instead of the number 4. Change-Id: I4b0ade1cd0b4b9cdb59f90f8d455269d0b69ed86 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56835 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 3d231b6..816df05 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -258,7 +258,7 @@ acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR(0); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); - acpigen_write_name_integer("_S0W", 4); + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); dsd = acpi_dp_new_table("_DSD"); pkg = acpi_dp_new_table(PCIE_RTD3_STORAGE_UUID); -- To view, visit https://review.coreboot.org/c/coreboot/+/56835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b0ade1cd0b4b9cdb59f90f8d455269d0b69ed86 Gerrit-Change-Number: 56835 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/uart/acpi: Update _S0W return value to D3hot
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56834 ) Change subject: drivers/uart/acpi: Update _S0W return value to D3hot ...................................................................... drivers/uart/acpi: Update _S0W return value to D3hot In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most UARTs that do have wake capabilities support wake from D3hot rather than D3cold. BUG=b:187228954 TEST=compile Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56834 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/uart/acpi/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/drivers/uart/acpi/acpi.c b/src/drivers/uart/acpi/acpi.c index d4b14aa..3081182 100644 --- a/src/drivers/uart/acpi/acpi.c +++ b/src/drivers/uart/acpi/acpi.c @@ -89,7 +89,7 @@ /* Wake capabilities */ if (config->wake) { - acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); acpigen_write_PRW(config->wake, SLP_TYP_S3); }; -- To view, visit https://review.coreboot.org/c/coreboot/+/56834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400 Gerrit-Change-Number: 56834 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/spi/acpi: Update _S0W return value to D3hot
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56833 ) Change subject: drivers/spi/acpi: Update _S0W return value to D3hot ...................................................................... drivers/spi/acpi: Update _S0W return value to D3hot In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most SPI peripherals that do have wake capabilities support wake from D3hot rather than D3cold. This also allows coreboot to expose a power resource to perform power sequencing for a SPI peripheral that is intended to retain power in S3/S0ix. If support for a device with d3cold wake support is needed, it could be added in later as an option. BUG=b:187228954 TEST=compile Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/spi/acpi/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index b23bc9d..abebd88 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -125,7 +125,7 @@ /* Wake capabilities */ if (config->wake) { - acpigen_write_name_integer("_S0W", 4); + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); acpigen_write_PRW(config->wake, 3); }; -- To view, visit https://review.coreboot.org/c/coreboot/+/56833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577 Gerrit-Change-Number: 56833 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/da7219: Update _S0W to D3hot
by Tim Wawrzynczak (Code Review) 09 Aug '21

09 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56832 ) Change subject: drivers/i2c/da7219: Update _S0W to D3hot ...................................................................... drivers/i2c/da7219: Update _S0W to D3hot The DA7219 does not support wake from D3cold, therefore update the return value of _S0W from D3cold to D3hot. BUG=b:187228954 TEST=compile Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/i2c/da7219/da7219.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 0423460..80c5272 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -36,7 +36,7 @@ acpigen_write_name_string("_HID", DA7219_ACPI_HID); acpigen_write_name_integer("_UID", 1); acpigen_write_name_string("_DDN", dev->chip_ops->name); - acpigen_write_name_integer("_S0W", 4); + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); acpigen_write_STA(acpi_device_status(dev)); /* Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2 Gerrit-Change-Number: 56832 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit August 2021