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Change subject: soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56867/comment/0e09f5af_4cebd673
PS2, Line 682:
> Probably would be good to explicitly set `SkipSsidProgramming` to 0 here as well.
Done
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Change subject: soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/tigerlake/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125939):
https://review.coreboot.org/c/coreboot/+/56867/comment/b080610f_6fd44d76
PS3, Line 640: uint64_t :4;
space prohibited before that ':' (ctx:WxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125939):
https://review.coreboot.org/c/coreboot/+/56867/comment/3a00b51c_703e5e97
PS3, Line 642: uint64_t :16;
space prohibited before that ':' (ctx:WxV)
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56867
to look at the new patch set (#3).
Change subject: soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
......................................................................
soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.
A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").
The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.
TGL also introduces parameters for customizing the default SVID:SSID.
These must be set or it will still use the FSP defaults.
Tested by checking lspci output on System76 darp7 (TGL-U).
References:
- b1fa231d76a ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S")
- TigerLake FSP Integration Guide
- Intel Document #631120-001
Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/56867/3
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/amd/common...spi: Add SPI config to Kconfig
......................................................................
soc/amd/common...spi: Add SPI config to Kconfig
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=None yet.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
---
M src/soc/amd/common/block/spi/Kconfig
1 file changed, 44 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56884/2
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Change subject: mb/google/guybrush: Update GPIOs for fingerprint
......................................................................
mb/google/guybrush: Update GPIOs for fingerprint
Add mainboard finalize and shutdown call to match zork.
Deassert EN_PWR_FP in bootblock, power up correctly in finalize.
| Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume |
|-----------|--------------|-----------|----------------------|
| Bootblock | **Low** | **Low** | Maintain High / High |
| Romstage | Low | Low | Maintain High / High |
| Ramstage | Low | **High** | Maintain High / High |
| Finalize | **High** | High | |
| Shutdown | **Low** | **Low** | |
BUG=b:191694480
TEST=Build, verify GPIO configuration.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43
---
M src/mainboard/google/guybrush/mainboard.c
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
3 files changed, 51 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56499/6
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Hello build bot (Jenkins), Paul Menzel, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/google/guybrush: Update GPIOs for fingerprint
......................................................................
mb/google/guybrush: Update GPIOs for fingerprint
Add mainboard finalize and shutdown call to match zork.
Deassert EN_PWR_FP in bootblock, power up correctly in finalize.
| Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume |
|-----------|--------------|-----------|----------------------|
| Bootblock | **Low** | **Low** | Maintain High / High |
| Romstage | Low | Low | Maintain High / High |
| Ramstage | Low | **High** | Maintain High / High |
| Finalize | **High** | High | |
| Shutdown | **Low** | **Low** | |
BUG=b:191694480
TEST=Build, verify GPIO configuration.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43
---
M src/mainboard/google/guybrush/mainboard.c
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
3 files changed, 53 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56499/5
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52580 )
Change subject: MAINTAINERS: Add Tim Crawford as a maintainer for System76
......................................................................
Patch Set 3: Code-Review+2
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Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56884 )
Change subject: soc/amd/common...spi: Add SPI config to Kconfig
......................................................................
soc/amd/common...spi: Add SPI config to Kconfig
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=None yet.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
---
M src/soc/amd/common/block/spi/Kconfig
1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56884/1
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig
index eb5412f..dd190f1 100644
--- a/src/soc/amd/common/block/spi/Kconfig
+++ b/src/soc/amd/common/block/spi/Kconfig
@@ -17,6 +17,7 @@
config EFS_SPI_READ_MODE
int
range 0 7
+ default 0 if EM100
default 2
help
SPI read mode to be programmed by the PSP.
@@ -35,6 +36,7 @@
config EFS_SPI_SPEED
int
range 0 5
+ default 3 if EM100
default 0
help
SPI Fast Speed to be programmed by the PSP.
@@ -56,3 +58,43 @@
0: Board does not use Micron parts
1: Board always uses Micron parts
2: Micron parts are optional
+
+config NORMAL_READ_SPI_SPEED
+ range 0 5
+ default 3 if EM100
+ default 1
+ help
+ SPI Normal Speed to be programmed by coreboot.
+ 0: 66.66Mhz
+ 1: 33.33MHz
+ 2: 22.22MHz
+ 3: 16.66MHz
+ 4: 100MHz
+ 5: 800KHz
+
+config ALT_SPI_SPEED
+ int
+ range 0 5
+ default 3 if EM100
+ default 0
+ help
+ SPI ALT Speed to be programmed by coreboot.
+ 0: 66.66Mhz
+ 1: 33.33MHz
+ 2: 22.22MHz
+ 3: 16.66MHz
+ 4: 100MHz
+ 5: 800KHz
+
+config TPM_SPI_SPEED
+ range 0 5
+ default 3 if EM100
+ default 0
+ help
+ SPI TPM Speed to be programmed by coreboot.
+ 0: 66.66Mhz
+ 1: 33.33MHz
+ 2: 22.22MHz
+ 3: 16.66MHz
+ 4: 100MHz
+ 5: 800KHz
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Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55969 )
Change subject: mb/intel/adlrvp: Support VBT binaries for LP4 and LP5
......................................................................
mb/intel/adlrvp: Support VBT binaries for LP4 and LP5
This will enable to include multiple VBT binaries in a single image
and load corresponding file according to HW configuration.
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969
Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/intel/adlrvp/mainboard.c
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Bora Guvendik: Looks good to me, approved
Bernardo Perez Priego: Looks good to me, but someone else must approve
Anil Kumar K: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index 1e1e318..fd0a9ba 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -68,10 +68,13 @@
switch (sku_id) {
case ADL_P_LP5_1:
case ADL_P_LP5_2:
+ case ADL_M_LP5:
return "vbt_adlrvp_lp5.bin";
case ADL_P_DDR5_1:
case ADL_P_DDR5_2:
return "vbt_adlrvp_ddr5.bin";
+ case ADL_M_LP4:
+ return "vbt_adlrvp_lp4.bin";
default:
return "vbt.bin";
}
--
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