Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56857 )
Change subject: util/spd_tools/lp4x: Update README
......................................................................
util/spd_tools/lp4x: Update README
The lp4x spd_tools also support Alder Lake (ADL), so update the the
README to reflect this fact.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Iedb1ea1c3558e5f179feac2c725667db5b327b2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56857
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/spd_tools/lp4x/README.md
1 file changed, 10 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/util/spd_tools/lp4x/README.md b/util/spd_tools/lp4x/README.md
index e614f25..d74ed6b 100644
--- a/util/spd_tools/lp4x/README.md
+++ b/util/spd_tools/lp4x/README.md
@@ -1,15 +1,16 @@
# LPDDR4x SPD tools README
Tools for generating SPD files for LPDDR4x memory used in memory down
-configurations on Intel Tiger Lake (TGL) and Jasper Lake (JSL) based
-platforms. These tools generate SPDs following JESD209-4C
-specification and Intel recommendations (doc #616599, #610202) for
-LPDDR4x SPD.
+configurations on Intel Tiger Lake (TGL), Jasper Lake (JSL), and Alder
+Lake (ADL) based platforms. These tools generate SPDs following
+JESD209-4C specification and Intel recommendations (doc #616599,
+#610202, #634730) for LPDDR4x SPD.
-There are two tools provided that assist TGL and JSL based mainboards
-to generate SPDs and Makefile to integrate these SPDs in coreboot
-build. These tools can also be used to allocate DRAM IDs (configure
-DRAM hardware straps) for any LPDDR4x memory part used by the board.
+There are two tools provided that assist TGL, JSL and ADL based
+mainboards to generate SPDs and Makefile to integrate these SPDs in
+coreboot build. These tools can also be used to allocate DRAM IDs
+(configure DRAM hardware straps) for any LPDDR4x memory part used by the
+board.
* gen_spd.go: Generates de-duplicated SPD files using a global memory
part list provided by the mainboard in JSON format. Additionally,
@@ -32,7 +33,7 @@
attributes as per the datasheet. This is the list of all known
LPDDR4x memory parts irrespective of their usage on the board.
* SoC platform name for which the SPDs are being generated. Currently
- supported platform names are `TGL` and `JSL`.
+ supported platform names are `TGL`, `JSL` and `ADL`.
Input JSON file requires the following two fields for every memory part:
* `name`: Name of the memory part
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53903 )
Change subject: libpayload: Add MMIO support in PCI lib
......................................................................
Patch Set 30:
(2 comments)
File payloads/libpayload/drivers/pci.c:
https://review.coreboot.org/c/coreboot/+/53903/comment/9a703c35_7ee1f5b4
PS22, Line 35: #if CONFIG(LP_MMCONF_SUPPORT)
: void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + reg;
: return read8(cfg_addr);
: #endif
: outl(device | (reg & ~3), 0xCF8);
: return inb(0xCFC + (reg & 3));
> Below API's are already present in pci.c file.
These are currently not present in ToT coreboot.
> are you referring "pci_read/write_config8/16/32" in pci.c file ?
I meant pci_mmio_{read|write}_config* ops to be defined that perform config space access using MMIO operations.
> Is my analysis is right on above comment ? Please let me know, I will incorporate the changes in next version patch.
Yes, your idea about using MMIO ops if MMIO base address is present and fallback to IO ops (only on x86) if no MMIO base address seems right.
File payloads/libpayload/drivers/pci_ops.c:
https://review.coreboot.org/c/coreboot/+/53903/comment/a5e75d7b_2877ef8d
PS28, Line 37: u32 devfn = ((dev >> 3) & 0x1f) | (dev & 0x07);
> Hi Furquan, […]
Makes sense. I have been also looking at how things are done in the Linux kernel and I like the idea of having a callback in the common code that allows the platform to perform any bus mapping if required. Something like `pci_map_bus()` that can configure the bus as required and return the MMIO address for the 4K config space of the device. For ECAM, this can use MMCONFIG. For other platforms (e.g. QCOM), you can use the callback to perform ATU configuration and return appropriate address. Does this make sense to you?
We would need this change both in coreboot and libpayload.
On that note, I think `MMCONF_SUPPORT` is not really the right option for qualcomm platforms. This is what I am thinking:
* There are two ways to access PCI config space - I/O access and MMIO access
* For MMIO access, PCI spec defines ECAM which is what the MMCONF_SUPPORT is about. However, the PCI spec provides flexibility to the platform if it wants to design the configuration window differently.
Thus, for a qualcomm platform, you would need MMIO access mechanism with a customized way of getting to the config window.
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Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56861 )
Change subject: 3rdparty/intel-microcode: Update submodule to 20210608 release
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56861/comment/4cd05a14_a242de90
PS1, Line 10:
> Tested how?
Is there anything specifically coreboot related that needs testing (and how)?
I can put a few boards I boot on.
Otherwise I'd say the package has been out for 2 months, with no bugs reported on Fedora or Arch against the release. Some Ubuntu users reported an issue with iwlwifi on CFL-H [1], but my CFL-H board doesn't have this issue.
[1]: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/…
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Hello build bot (Jenkins), Furquan Shaikh, Jack Rosenthal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56883
to look at the new patch set (#2).
Change subject: elogtool: add "clear" command
......................................................................
elogtool: add "clear" command
Adds "clear" command to cbfsutil/elogtool tool.
"clear" clears the RW_ELOG using flashrom with ELOG_TYPE_EOL.
And inserts a ELOG_TYPE_LOG_CLEAR event.
Usage:
$ elogtool clear
BUG=b:172210863
Change-Id: Ia28a6eb34c82103ab078a0841b022e2e5e430585
Signed-off-by: Ricardo Quesada <ricardoq(a)google.com>
---
M src/commonlib/bsd/elog.c
M src/commonlib/bsd/include/commonlib/bsd/elog.h
M src/drivers/elog/elog.c
M util/cbfstool/elogtool.c
M util/cbfstool/eventlog.c
M util/cbfstool/eventlog.h
6 files changed, 172 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/56883/2
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Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56828 )
Change subject: mb/google/dedede/var/storo: Fixed iasl can not run on Dut
......................................................................
Patch Set 1: Code-Review+2
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Change subject: elogtool: add "clear" command
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
Hi Jack & Furquan, could you PTAL?
File src/commonlib/bsd/elog.c:
https://review.coreboot.org/c/coreboot/+/56883/comment/ce5ad4e7_7186f8a0
PS1, Line 50: static inline uint8_t mybin2bcd(uint8_t val)
: {
: return ((val / 10) << 4) | (val % 10);
: }
:
Already defined here:
https://github.com/coreboot/coreboot/blob/master/src/include/bcd.h
But licenced under GPL.
Should I rewrite it from scratch and license it under BSD? (or perhaps just copy it from Mosys which is BSD-based)
https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/ma…
... and of course, change existing code to use the new include file?
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