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Change subject: mb/intel/adlrvp: Add support for DDR5 MR SKU
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56881/comment/4b39c642_7a7c5da5
PS2, Line 63: ADL_P_DDR5_2
> looks like SPD chip is not there on this board/sku so you need to pass the hardcoded SPD hex table ?
Yes, Subrata. Here is the spd hex data -
src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex
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Change subject: mb/intel/adlrvp: Add support for DDR5 MR SKU
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56881/comment/9d2d4824_bff1df06
PS2, Line 63: ADL_P_DDR5_2
looks like SPD chip is not there on this board/sku so you need to pass the hardcoded SPD hex table ?
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Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56881
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Add support for DDR5 MR SKU
......................................................................
mb/intel/adlrvp: Add support for DDR5 MR SKU
DDR5 Maple ridge SKU uses a Memory down DIMM configuration.
This CL adds support for the same.
TEST=Boot DDR5 MR SKU to OS.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/adlrvp/spd/Makefile.inc
A src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex
3 files changed, 41 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/56881/2
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Change subject: mb/google/brya/variants/gimble: Update GPIO for PP1800 DMIC enable
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56889/comment/a14f357d_9e707e04
PS1, Line 9: PP1800 DMIC
If this is supposed to be PP1800, do you also need to change FIT config to set GPP_D16 to 1.8V instead of 3.3V?
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Change subject: drivers/generic/alc1015: Add HID to support alc1019
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/generic/alc1015/chip.h:
https://review.coreboot.org/c/coreboot/+/56877/comment/628c560f_4646c23f
PS2, Line 6: const char *hid; /* ACPI _HID */
> WDYT about an enum, e.g.: […]
this can work as well. but if just use the hid... we don't have to maintain this driver if new IC coming. Since reltek don't want to maintain this...
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Change subject: mb/google/brya/variants/gimble: Update GPIO for PP1800 DMIC enable
......................................................................
Patch Set 1: Code-Review+1
This change is ready for review.
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Change subject: libpayload: Add MMIO support in PCI lib
......................................................................
Patch Set 30:
(1 comment)
Patchset:
PS30:
(P.S. There is similar effort ongoing from another vendor to enable PCIe support in coreboot and libpayload: https://review.coreboot.org/c/coreboot/+/56790. We should consolidate this into a single effort).
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Change subject: arch/arm64: Add PCI configuration interface
......................................................................
Patch Set 1:
(1 comment)
File src/arch/arm64/include/arch/pci_cfg.h:
https://review.coreboot.org/c/coreboot/+/56790/comment/c8f6a708_e37efdbb
PS1, Line 12: extern void *arch_pci_map_bus(u32 dev, u32 where, u8 size);
> Hi Furquan, […]
Hi Jianjun,
I have been looking at how things are done in the Linux kernel and I like the idea of having a callback in the common code that allows the platform to perform any bus mapping if required. Something like `pci_map_bus()` that can configure the bus as required and return the MMIO address for the 4K config space of the device. For ECAM, this can use MMCONFIG. For other platforms (e.g. Mediatek), you can use the callback to perform any required configuration and return appropriate address. I don't think we can change `struct device` in coreboot. Instead it will have to be a callback that the PCI MMIO ops make to get to the MMIO address.
Does this make sense to you?
We would need this change both in coreboot and libpayload.
(P.S. I noticed there is similar effort ongoing from another vendor to enable PCIe support in coreboot and libpayload: https://review.coreboot.org/c/coreboot/+/53903. We should consolidate this into a single effort).
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Change subject: mb/google/guybrush: Switch from 33MHz to 66MHz SPI Speed
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/56645/comment/ab459791_049f7f4f
PS3, Line 13: 33M
Thanks for the background, Kyosti! This is very helpful.
> everything through the SPI driver layer will use .altio_speed.
So, in that case do we need to change the altio speed if a normal read (as opposed to fast read) is being made by the SPI driver layer in coreboot?
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