coreboot-gerrit August 2021

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Change in coreboot[master]: mb/google/brya: Add I2C parameter
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56970 ) Change subject: mb/google/brya: Add I2C parameter ...................................................................... mb/google/brya: Add I2C parameter Add I2C parameters to make sure each bus speed is around 390kHz. BUG=b:188793264 TEST=Measure by scope. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Varshit B Pandya: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 8a779bc..3281902 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -95,19 +95,34 @@ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 900, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[3] = { .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/56970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0 Gerrit-Change-Number: 56970 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/kano: Configure GPIOs according to schematics
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56940 ) Change subject: mb/google/brya/variants/kano: Configure GPIOs according to schematics ...................................................................... mb/google/brya/variants/kano: Configure GPIOs according to schematics Update initial gpio configuration for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/mainboard/google/brya/variants/kano/Makefile.inc A src/mainboard/google/brya/variants/kano/gpio.c 2 files changed, 135 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/Makefile.inc b/src/mainboard/google/brya/variants/kano/Makefile.inc new file mode 100644 index 0000000..8fe978f --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c new file mode 100644 index 0000000..cc6a870 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D5 : SRCCLKREQ0# ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D18 : UART1_TXD ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> SAR1_INT_L */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : I2C7_SDA ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e Gerrit-Change-Number: 56940 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Configure EN_FCAM_PWR to high
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56882 ) Change subject: mb/google/brya: Configure EN_FCAM_PWR to high ...................................................................... mb/google/brya: Configure EN_FCAM_PWR to high Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17 as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and OFF by IPU driver while MIPI UFC probing. However USB UFC also requires 3.3V which is enabled by A17. This caused USB UFC enumeration to fail BUG=b:196014678 Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index fbe6323..a3cebae 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -37,7 +37,7 @@ /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_A17, 0, DEEP), + PAD_CFG_GPO(GPP_A17, 1, DEEP), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2 Gerrit-Change-Number: 56882 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/util/kconfig: Remove silentoldconfig
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56878 ) Change subject: Documentation/util/kconfig: Remove silentoldconfig ...................................................................... Documentation/util/kconfig: Remove silentoldconfig The "silentoldconfig" target has been removed in Linux 5.13's kconfig (CB:37152). As explained by Michal Marek at https://lkml.org/lkml/2011/8/31/189, the "silentoldconfig" target has become an internal interface and "oldconfig" is just as silent now. Therefore, correct the target for syntax checking. Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56878 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M Documentation/getting_started/kconfig.md 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Jakub Czapiga: Looks good to me, approved diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 819eb72..fff186e 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -1188,7 +1188,7 @@ ## Syntax Checking: The Kconfig utility does some basic syntax checking on the Kconfig tree. -Running "make silentoldconfig" will show any errors that the Kconfig utility +Running "make oldconfig" will show any errors that the Kconfig utility sees. ### util/kconfig_lint -- To view, visit https://review.coreboot.org/c/coreboot/+/56878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0 Gerrit-Change-Number: 56878 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarity
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56923 ) Change subject: mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarity ...................................................................... mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarity modify reset_gpio as active low to meet touchscreen spec BUG=b:195490284 BRANCH=none TEST=build coreboot and touchscreen works Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index caca16d..938766b 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -195,7 +195,7 @@ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C1)" + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" -- To view, visit https://review.coreboot.org/c/coreboot/+/56923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb Gerrit-Change-Number: 56923 Gerrit-PatchSet: 4 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: allow MKBP devices and disable TBMC device
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56903 ) Change subject: mb/google/brya: allow MKBP devices and disable TBMC device ...................................................................... mb/google/brya: allow MKBP devices and disable TBMC device Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Brya P1: Volume Up/Down buttons Signed-off-by: Boris Mittelberg <bmbm(a)google.com> Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h index c76274e..b346530 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h @@ -60,11 +60,11 @@ #define EC_ENABLE_ALS_DEVICE /* Enable Keyboard Backlight */ #define EC_ENABLE_KEYBOARD_BACKLIGHT +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -/* Enable Tablet switch */ -#define EC_ENABLE_TBMC_DEVICE /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728 Gerrit-Change-Number: 56903 Gerrit-PatchSet: 5 Gerrit-Owner: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Update GPIOs for fingerprint MCU
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56499 ) Change subject: mb/google/guybrush: Update GPIOs for fingerprint MCU ...................................................................... mb/google/guybrush: Update GPIOs for fingerprint MCU Add mainboard finalize and shutdown call to match zork. Deassert EN_PWR_FP in bootblock, power up correctly in finalize. | Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume | |-----------|--------------|-----------|----------------------| | Bootblock | **Low** | **Low** | Maintain High / High | | Romstage | Low | Low | Maintain High / High | | Ramstage | Low | **High** | Maintain High / High | | Finalize | **High** | High | | | Shutdown | **Low** | **Low** | | BUG=b:191694480 TEST=Build, verify GPIO configuration. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h 3 files changed, 46 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index e557802..3626157 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -176,7 +176,13 @@ pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); } +static void mainboard_final(void *chip_info) +{ + variant_finalize_gpios(); +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, + .final = mainboard_final, }; diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 352d0f5..559a86d 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -4,6 +4,8 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> +#include <delay.h> +#include <gpio.h> #include <soc/gpio.h> /* GPIO configuration in ramstage*/ @@ -31,8 +33,8 @@ PAD_SCI(GPIO_9, PULL_NONE, EDGE_HIGH), /* S0A3 */ PAD_NF(GPIO_10, S0A3, PULL_NONE), - /* SOC_FP_RST_L */ - PAD_GPO(GPIO_11, HIGH), + /* SOC_FP_RST_L - Brought high in finalize */ + PAD_GPO(GPIO_11, LOW), /* SLP_S3_GATED */ PAD_GPO(GPIO_12, LOW), /* GPIO_13 - GPIO_15: Not available */ @@ -285,6 +287,13 @@ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; +static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size) { *size = ARRAY_SIZE(pcie_gpio_table); @@ -334,6 +343,11 @@ const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size) { + if (acpi_get_sleep_type() == ACPI_S5) { + *size = ARRAY_SIZE(gpio_fp_shutdown_table); + return gpio_fp_shutdown_table; + } + *size = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } @@ -342,18 +356,31 @@ { if (acpi_get_sleep_type() == ACPI_S3) return; - /* - * SOC_FP_RST_L line is pulled high when platform comes out of reset. - * So, it is required to be driven low before enabling power to - * ensure that power sequencing for the FPMCU is met. - * However, as the FPMCU is initialized only on platform reset, - * the reset line should not be asserted in case of S3 resume. - */ + /* If the system is not resuming from S3, power off the FPMCU */ static const struct soc_amd_gpio fpmcu_bootblock_table[] = { /* SOC_FP_RST_L */ PAD_GPO(GPIO_11, LOW), /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), + PAD_GPO(GPIO_32, LOW), }; program_gpios(fpmcu_bootblock_table, ARRAY_SIZE(fpmcu_bootblock_table)); } + +__weak void variant_finalize_gpios(void) +{ + static const struct soc_amd_gpio disable_fpmcu_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), + }; + + if (variant_has_fpmcu()) { + if (acpi_get_sleep_type() == ACPI_S3) + return; + /* Deassert the FPMCU reset to enable the FPMCU */ + gpio_set(GPIO_11, 1); /* FPMCU_RST_L */ + } else { + program_gpios(disable_fpmcu_table, ARRAY_SIZE(disable_fpmcu_table)); + } +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 243f7ff..b9a7088 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -39,6 +39,9 @@ /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); +/* Finalize GPIOs, such as FPMCU power */ +void variant_finalize_gpios(void); + void variant_fpmcu_reset(void); bool variant_has_fpmcu(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/56499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Gerrit-Change-Number: 56499 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Mark ECC as working on Sandy Bridge
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56977 ) Change subject: Documentation: Mark ECC as working on Sandy Bridge ...................................................................... Documentation: Mark ECC as working on Sandy Bridge Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56977 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M Documentation/northbridge/intel/sandybridge/nri_features.md 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md index d700b54..670fcb6 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_features.md +++ b/Documentation/northbridge/intel/sandybridge/nri_features.md @@ -84,6 +84,6 @@ +---------------------------+----------------------+-------------+---------+---------------------+ | **ECC support** | +---------------------------+----------------------+-------------+---------+---------------------+ -| ECC | yes | no | | | +| ECC | yes | yes | yes | Since coreboot 4.13 | +---------------------------+----------------------+-------------+---------+---------------------+ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/56977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812 Gerrit-Change-Number: 56977 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Mark ECC as working on Sandy Bridge
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Attention is currently required from: Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56977 ) Change subject: Documentation: Mark ECC as working on Sandy Bridge ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812 Gerrit-Change-Number: 56977 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 16 Aug 2021 14:46:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add TGL-H PCI IDs
by Tim Crawford (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Patrick Rudolph. Hello build bot (Jenkins), Jeremy Soller, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56900 to look at the new patch set (#2). Change subject: soc/intel/common: Add TGL-H PCI IDs ...................................................................... soc/intel/common: Add TGL-H PCI IDs Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/drivers/intel/ish/ish.c M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/ipu/ipu.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 24 files changed, 167 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/56900/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Gerrit-Change-Number: 56900 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2021